The cirros image was rebuilt against the 3.13.0-83 kernel, drivers e1000e, igbvf...
[packages/trusty/cirros-testvm.git] / cirros-testvm / src-cirros / buildroot-2015.05 / package / netcat / 0001-signed-bit-counting.patch
diff --git a/cirros-testvm/src-cirros/buildroot-2015.05/package/netcat/0001-signed-bit-counting.patch b/cirros-testvm/src-cirros/buildroot-2015.05/package/netcat/0001-signed-bit-counting.patch
new file mode 100644 (file)
index 0000000..e29da31
--- /dev/null
@@ -0,0 +1,30 @@
+# Fix the endian-specific bit-counting code so that it works.
+# SF:1068324 "netcat_flag_count() fix"
+#   http://sourceforge.net/tracker/?func=detail&aid=1205729&group_id=52204&atid=466046
+# SF:1205729 "doen't work on arm linux platform":
+#   http://sourceforge.net/tracker/?func=detail&aid=1068324&group_id=52204&atid=466046
+
+Index: netcat-0.7.1/src/flagset.c
+===================================================================
+--- netcat-0.7.1.orig/src/flagset.c    2010-07-19 13:51:46.000000000 +0100
++++ netcat-0.7.1/src/flagset.c 2010-07-19 13:52:27.000000000 +0100
+@@ -134,7 +134,7 @@
+ int netcat_flag_count(void)
+ {
+-  register char c;
++  register unsigned char c;
+   register int i;
+   int ret = 0;
+@@ -154,8 +154,8 @@
+       Assumed that the bit number 1 is the sign, and that we will shift the
+       bit 1 (or the bit that takes its place later) until the the most right,
+       WHY it has to keep the wrong sign? */
+-      ret -= (c >> 7);
+-      c <<= 1;
++      ret += c&1;
++      c>>=1;
+     }
+   }