cirros-testvm/src-cirros/buildroot-2015.05/board/calao/usb-a9g20-lpw/at91bootstrap-1.16-usb-a9g20-lpw.patch

   1 From 8d84757d5170969e8bdfebc7951f43c5aa2b05fd Mon Sep 17 00:00:00 2001
   2 From: Gregory Hermant <gregory.hermant@calao-systems.com>
   3 Date: Fri, 6 Jul 2012 16:32:47 +0200
   4 Subject: [PATCH] Add support for the Calao-systems USB-A9G20-LPW
   5
   6
   7 Signed-off-by: Gregory Hermant <gregory.hermant@calao-systems.com>
   8 ---
   9  board/usb_a9g20_lpw/nandflash/Makefile        |  121 ++++++++++
  10  board/usb_a9g20_lpw/nandflash/usb-a9g20-lpw.h |  112 +++++++++
  11  board/usb_a9g20_lpw/usb_a9g20_lpw.c           |  303 +++++++++++++++++++++++++
  12  crt0_gnu.S                                    |    7 +
  13  include/part.h                                |    6 +-
  14  5 files changed, 548 insertions(+), 1 deletions(-)
  15  create mode 100644 board/usb_a9g20_lpw/nandflash/Makefile
  16  create mode 100644 board/usb_a9g20_lpw/nandflash/usb-a9g20-lpw.h
  17  create mode 100644 board/usb_a9g20_lpw/usb_a9g20_lpw.c
  18
  19 diff --git a/board/usb_a9g20_lpw/nandflash/Makefile b/board/usb_a9g20_lpw/nandflash/Makefile
  20 new file mode 100644
  21 index 0000000..8c9d99a
  22 --- /dev/null
  23 +++ b/board/usb_a9g20_lpw/nandflash/Makefile
  24 @@ -0,0 +1,121 @@
  25 +# TODO: set this appropriately for your local toolchain
  26 +ifndef ERASE_FCT
  27 +ERASE_FCT=rm -f
  28 +endif
  29 +ifndef CROSS_COMPILE
  30 +CROSS_COMPILE=arm-elf-
  31 +endif
  32 +
  33 +TOOLCHAIN=gcc
  34 +
  35 +BOOTSTRAP_PATH=../../..
  36 +
  37 +# NandFlashBoot Configuration for USB-A9G20-LPW
  38 +
  39 +# Target name (case sensitive!!!)
  40 +TARGET=AT91SAM9G20
  41 +# Board name (case sensitive!!!)
  42 +BOARD=usb_a9g20_lpw
  43 +# Link Address and Top_of_Memory
  44 +LINK_ADDR=0x200000
  45 +TOP_OF_MEMORY=0x301000
  46 +# Name of current directory
  47 +PROJECT=nandflash
  48 +
  49 +ifndef BOOT_NAME
  50 +BOOT_NAME=$(PROJECT)_$(BOARD)
  51 +endif
  52 +
  53 +INCL=./$(BOOTSTRAP_PATH)/board/$(BOARD)/$(PROJECT)
  54 +
  55 +ifeq ($(TOOLCHAIN), gcc)
  56 +
  57 +AS=$(CROSS_COMPILE)gcc
  58 +CC=$(CROSS_COMPILE)gcc
  59 +LD=$(CROSS_COMPILE)gcc
  60 +NM= $(CROSS_COMPILE)nm
  61 +SIZE=$(CROSS_COMPILE)size
  62 +OBJCOPY=$(CROSS_COMPILE)objcopy
  63 +OBJDUMP=$(CROSS_COMPILE)objdump
  64 +CCFLAGS=-g -mcpu=arm926ej-s -Os -Wall -D$(TARGET) -D$(BOARD) -I$(INCL)
  65 +ASFLAGS=-g -mcpu=arm926ej-s -c -Os -Wall -D$(TARGET) -D$(BOARD) -I$(INCL) -DTOP_OF_MEM=$(TOP_OF_MEMORY)
  66 +
  67 +# Linker flags.
  68 +#  -Wl,...:     tell GCC to pass this to linker.
  69 +#    -Map:      create map file
  70 +#    --cref:    add cross reference to map file
  71 +LDFLAGS+=-nostartfiles -nostdlib -Wl,-Map=$(BOOT_NAME).map,--cref
  72 +LDFLAGS+=-T $(BOOTSTRAP_PATH)/elf32-littlearm.lds -Ttext $(LINK_ADDR)
  73 +OBJS=crt0_gnu.o
  74 +
  75 +endif
  76 +
  77 +OBJS+=\
  78 +       $(BOARD).o \
  79 +       main.o \
  80 +       gpio.o \
  81 +       pmc.o \
  82 +       debug.o \
  83 +       sdramc.o \
  84 +       nandflash.o \
  85 +       _udivsi3.o \
  86 +       _umodsi3.o \
  87 +       div0.o \
  88 +       udiv.o \
  89 +       string.o
  90 +
  91 +rebuild: clean all
  92 +
  93 +all:   $(BOOT_NAME)
  94 +
  95 +ifeq ($(TOOLCHAIN), gcc)
  96 +$(BOOT_NAME): $(OBJS)
  97 +       $(LD) $(LDFLAGS) -n -o $(BOOT_NAME).elf $(OBJS)
  98 +       $(OBJCOPY) --strip-debug --strip-unneeded $(BOOT_NAME).elf -O binary $(BOOT_NAME).bin
  99 +endif
 100 +
 101 +
 102 +$(BOARD).o: $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c
 103 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c -o $(BOARD).o
 104 +
 105 +main.o: $(BOOTSTRAP_PATH)/main.c
 106 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/main.c -o main.o
 107 +
 108 +gpio.o: $(BOOTSTRAP_PATH)/driver/gpio.c
 109 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/gpio.c -o gpio.o
 110 +
 111 +pmc.o:  $(BOOTSTRAP_PATH)/driver/pmc.c
 112 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/pmc.c -o pmc.o
 113 +
 114 +debug.o: $(BOOTSTRAP_PATH)/driver/debug.c
 115 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/debug.c -o debug.o
 116 +
 117 +sdramc.o:  $(BOOTSTRAP_PATH)/driver/sdramc.c
 118 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/sdramc.c -o sdramc.o
 119 +
 120 +dataflash.o:  $(BOOTSTRAP_PATH)/driver/dataflash.c
 121 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/dataflash.c -o dataflash.o
 122 +
 123 +nandflash.o:  $(BOOTSTRAP_PATH)/driver/nandflash.c
 124 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/nandflash.c -o nandflash.o
 125 +
 126 +crt0_gnu.o:  $(BOOTSTRAP_PATH)/crt0_gnu.S
 127 +       $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/crt0_gnu.S -o crt0_gnu.o
 128 +
 129 +div0.o:  $(BOOTSTRAP_PATH)/lib/div0.c
 130 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/div0.c -o div0.o
 131 +
 132 +string.o:  $(BOOTSTRAP_PATH)/lib/string.c
 133 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/string.c -o string.o
 134 +
 135 +udiv.o:  $(BOOTSTRAP_PATH)/lib/udiv.c
 136 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/udiv.c -o udiv.o
 137 +
 138 +_udivsi3.o:  $(BOOTSTRAP_PATH)/lib/_udivsi3.S
 139 +       $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_udivsi3.S -o _udivsi3.o
 140 +
 141 +_umodsi3.o:  $(BOOTSTRAP_PATH)/lib/_umodsi3.S
 142 +       $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_umodsi3.S -o _umodsi3.o
 143 +
 144 +clean:
 145 +       $(ERASE_FCT) *.o *.bin *.elf *.map
 146 diff --git a/board/usb_a9g20_lpw/nandflash/usb-a9g20-lpw.h b/board/usb_a9g20_lpw/nandflash/usb-a9g20-lpw.h
 147 new file mode 100644
 148 index 0000000..c0bdc6e
 149 --- /dev/null
 150 +++ b/board/usb_a9g20_lpw/nandflash/usb-a9g20-lpw.h
 151 @@ -0,0 +1,112 @@
 152 +/* ----------------------------------------------------------------------------
 153 + *         ATMEL Microcontroller Software Support  -  ROUSSET  -
 154 + * ----------------------------------------------------------------------------
 155 + * Copyright (c) 2008, Atmel Corporation
 156 +
 157 + * All rights reserved.
 158 + *
 159 + * Redistribution and use in source and binary forms, with or without
 160 + * modification, are permitted provided that the following conditions are met:
 161 + *
 162 + * - Redistributions of source code must retain the above copyright notice,
 163 + * this list of conditions and the disclaimer below.
 164 + *
 165 + * Atmel's name may not be used to endorse or promote products derived from
 166 + * this software without specific prior written permission.
 167 + *
 168 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 169 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 170 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 171 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 172 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 173 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 174 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 175 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 176 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 177 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 178 + * ----------------------------------------------------------------------------
 179 + * File Name           : usb-a9g20-lpw.h
 180 + * Object              :
 181 + * Creation            : GH July 6th 2012
 182 + *-----------------------------------------------------------------------------
 183 + */
 184 +#ifndef _USB_A9G20_LPW_H
 185 +#define _USB_A9G20_LPW_H
 186 +
 187 +/* ******************************************************************* */
 188 +/* PMC Settings                                                        */
 189 +/*                                                                     */
 190 +/* The main oscillator is enabled as soon as possible in the c_startup */
 191 +/* and MCK is switched on the main oscillator.                         */
 192 +/* PLL initialization is done later in the hw_init() function          */
 193 +/* ******************************************************************* */
 194 +#define MASTER_CLOCK           (133000000)
 195 +#define PLL_LOCK_TIMEOUT       1000000
 196 +
 197 +/* Set PLLA to 798Mhz */
 198 +#define PLLA_SETTINGS  0x20843F02
 199 +#define PLLB_SETTINGS  0x100F3F02
 200 +
 201 +/* Switch MCK on PLLA output PCK = PLLA/2 = 3 * MCK */
 202 +#define MCKR_SETTINGS          0x1300
 203 +#define MCKR_CSS_SETTINGS      (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS)
 204 +
 205 +/* ******************************************************************* */
 206 +/* NandFlash Settings                                                  */
 207 +/*                                                                     */
 208 +/* ******************************************************************* */
 209 +#define AT91C_SMARTMEDIA_BASE  0x40000000
 210 +
 211 +#define AT91_SMART_MEDIA_ALE    (1 << 21)      /* our ALE is AD21 */
 212 +#define AT91_SMART_MEDIA_CLE    (1 << 22)      /* our CLE is AD22 */
 213 +
 214 +#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
 215 +#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
 216 +
 217 +#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
 218 +
 219 +
 220 +/* ******************************************************************** */
 221 +/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 133000000.*/
 222 +/* Please refer to SMC section in AT91SAM9 datasheet to learn how      */
 223 +/* to generate these values.                                           */
 224 +/* ******************************************************************** */
 225 +#define AT91C_SM_NWE_SETUP     (2 << 0)
 226 +#define AT91C_SM_NCS_WR_SETUP  (0 << 8)
 227 +#define AT91C_SM_NRD_SETUP     (2 << 16)
 228 +#define AT91C_SM_NCS_RD_SETUP  (0 << 24)
 229 +
 230 +#define AT91C_SM_NWE_PULSE     (4 << 0)
 231 +#define AT91C_SM_NCS_WR_PULSE  (4 << 8)
 232 +#define AT91C_SM_NRD_PULSE     (4 << 16)
 233 +#define AT91C_SM_NCS_RD_PULSE  (4 << 24)
 234 +
 235 +#define AT91C_SM_NWE_CYCLE     (7 << 0)
 236 +#define AT91C_SM_NRD_CYCLE     (7 << 16)
 237 +
 238 +#define AT91C_SM_TDF           (3 << 16)
 239 +
 240 +/* ******************************************************************* */
 241 +/* BootStrap Settings                                                  */
 242 +/*                                                                     */
 243 +/* ******************************************************************* */
 244 +#define IMG_ADDRESS            0x20000                 /* Image Address in NandFlash */
 245 +#define        IMG_SIZE                0x40000                 /* Image Size in NandFlash */
 246 +
 247 +#define MACH_TYPE              0x731                   /* USB-A9G20 */
 248 +#define JUMP_ADDR              0x23F00000              /* Final Jump Address */
 249 +
 250 +/* ******************************************************************* */
 251 +/* Application Settings                                                */
 252 +/* ******************************************************************* */
 253 +#undef CFG_DEBUG
 254 +#undef CFG_DATAFLASH
 255 +
 256 +#define CFG_NANDFLASH
 257 +#undef NANDFLASH_SMALL_BLOCKS  /* NANDFLASH_LARGE_BLOCKS used instead */
 258 +#undef  CFG_NANDFLASH_RECOVERY
 259 +
 260 +#define        CFG_SDRAM
 261 +#define        CFG_HW_INIT
 262 +
 263 +#endif /* _USB_A9G20_LPW_H */
 264 diff --git a/board/usb_a9g20_lpw/usb_a9g20_lpw.c b/board/usb_a9g20_lpw/usb_a9g20_lpw.c
 265 new file mode 100644
 266 index 0000000..c372307
 267 --- /dev/null
 268 +++ b/board/usb_a9g20_lpw/usb_a9g20_lpw.c
 269 @@ -0,0 +1,303 @@
 270 +/* ----------------------------------------------------------------------------
 271 + *         ATMEL Microcontroller Software Support  -  ROUSSET  -
 272 + * ----------------------------------------------------------------------------
 273 + * Copyright (c) 2008, Atmel Corporation
 274 +
 275 + * All rights reserved.
 276 + *
 277 + * Redistribution and use in source and binary forms, with or without
 278 + * modification, are permitted provided that the following conditions are met:
 279 + *
 280 + * - Redistributions of source code must retain the above copyright notice,
 281 + * this list of conditions and the disclaimer below.
 282 + *
 283 + * Atmel's name may not be used to endorse or promote products derived from
 284 + * this software without specific prior written permission.
 285 + *
 286 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 287 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 288 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 289 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 290 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 291 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 292 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 293 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 294 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 295 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 296 + * ----------------------------------------------------------------------------
 297 + * File Name           : usb_a9g20_lpw.c
 298 + * Object              :
 299 + * Creation            : GH July 6th 2012
 300 + *-----------------------------------------------------------------------------
 301 + */
 302 +#include "../../include/part.h"
 303 +#include "../../include/gpio.h"
 304 +#include "../../include/pmc.h"
 305 +#include "../../include/debug.h"
 306 +#include "../../include/sdramc.h"
 307 +#include "../../include/main.h"
 308 +#ifdef CFG_NANDFLASH
 309 +#include "../../include/nandflash.h"
 310 +#endif
 311 +#ifdef CFG_DATAFLASH
 312 +#include "../../include/dataflash.h"
 313 +#endif
 314 +
 315 +static inline unsigned int get_cp15(void)
 316 +{
 317 +       unsigned int value;
 318 +       __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value));
 319 +       return value;
 320 +}
 321 +
 322 +static inline void set_cp15(unsigned int value)
 323 +{
 324 +       __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value));
 325 +}
 326 +
 327 +#ifdef CFG_HW_INIT
 328 +/*----------------------------------------------------------------------------*/
 329 +/* \fn    hw_init                                                            */
 330 +/* \brief This function performs very low level HW initialization            */
 331 +/* This function is invoked as soon as possible during the c_startup         */
 332 +/* The bss segment must be initialized                                       */
 333 +/*----------------------------------------------------------------------------*/
 334 +void hw_init(void)
 335 +{
 336 +       unsigned int cp15;
 337 +
 338 +       /* Configure PIOs */
 339 +       const struct pio_desc hw_pio[] = {
 340 +#ifdef CFG_DEBUG
 341 +               {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
 342 +               {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
 343 +#endif
 344 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 345 +       };
 346 +
 347 +       /* Disable watchdog */
 348 +       writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
 349 +
 350 +       /* At this stage the main oscillator is supposed to be enabled
 351 +        * PCK = MCK = MOSC */
 352 +       writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
 353 +
 354 +       /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
 355 +       pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
 356 +
 357 +       /* PCK = PLLA/2 = 3 * MCK */
 358 +       pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
 359 +       /* Switch MCK on PLLA output */
 360 +       pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
 361 +
 362 +       /* Configure PLLB */
 363 +       pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
 364 +
 365 +       /* Configure CP15 */
 366 +       cp15 = get_cp15();
 367 +       cp15 |= I_CACHE;
 368 +       set_cp15(cp15);
 369 +
 370 +       /* Configure the PIO controller */
 371 +       pio_setup(hw_pio);
 372 +
 373 +       /* Configure the EBI Slave Slot Cycle to 64 */
 374 +       writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3));
 375 +
 376 +#ifdef CFG_DEBUG
 377 +       /* Enable Debug messages on the DBGU */
 378 +       dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
 379 +
 380 +       dbg_print("Start AT91Bootstrap...\n\r");
 381 +#endif /* CFG_DEBUG */
 382 +
 383 +#ifdef CFG_SDRAM
 384 +       /* Initialize the matrix (VDDIOSEL=0: memory voltage = 1.8V ) */
 385 +       writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA) & ~0x00010000) | AT91C_EBI_CS1A_SDRAMC , AT91C_BASE_CCFG + CCFG_EBICSA);
 386 +
 387 +       /* Configure SDRAM Controller */
 388 +       sdram_init(     AT91C_SDRAMC_NC_9  |
 389 +                               AT91C_SDRAMC_NR_13 |
 390 +                               AT91C_SDRAMC_CAS_3 |
 391 +                               AT91C_SDRAMC_NB_4_BANKS |
 392 +                               AT91C_SDRAMC_DBW_32_BITS |
 393 +                               AT91C_SDRAMC_TWR_3 |
 394 +                               AT91C_SDRAMC_TRC_9 |
 395 +                               AT91C_SDRAMC_TRP_3 |
 396 +                               AT91C_SDRAMC_TRCD_3 |
 397 +                               AT91C_SDRAMC_TRAS_6 |
 398 +                               AT91C_SDRAMC_TXSR_10,           /* Control Register */
 399 +                               (MASTER_CLOCK * 7)/1000000,     /* Refresh Timer Register */
 400 +                                AT91C_SDRAMC_MD_SDRAM);         /* SDRAM (no low power)   */
 401 +
 402 +#endif /* CFG_SDRAM */
 403 +}
 404 +#endif /* CFG_HW_INIT */
 405 +
 406 +#ifdef CFG_SDRAM
 407 +/*------------------------------------------------------------------------------*/
 408 +/* \fn    sdramc_hw_init                                                       */
 409 +/* \brief This function performs SDRAMC HW initialization                      */
 410 +/*------------------------------------------------------------------------------*/
 411 +void sdramc_hw_init(void)
 412 +{
 413 +       /* Configure PIOs */
 414 +/*     const struct pio_desc sdramc_pio[] = {
 415 +               {"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
 416 +               {"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
 417 +               {"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
 418 +               {"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
 419 +               {"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
 420 +               {"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
 421 +               {"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
 422 +               {"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
 423 +               {"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
 424 +               {"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
 425 +               {"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
 426 +               {"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
 427 +               {"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
 428 +               {"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
 429 +               {"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
 430 +               {"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
 431 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 432 +       };
 433 +*/
 434 +       /* Configure the SDRAMC PIO controller to output PCK0 */
 435 +/*     pio_setup(sdramc_pio); */
 436 +
 437 +       writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
 438 +       writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
 439 +
 440 +}
 441 +#endif /* CFG_SDRAM */
 442 +
 443 +#ifdef CFG_DATAFLASH
 444 +
 445 +/*------------------------------------------------------------------------------*/
 446 +/* \fn    df_recovery                                                          */
 447 +/* \brief This function erases DataFlash Page 0 if USR PB is pressed           */
 448 +/*        during boot sequence                                                 */
 449 +/*------------------------------------------------------------------------------*/
 450 +void df_recovery(AT91PS_DF pDf)
 451 +{
 452 +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
 453 +       /* Configure PIOs */
 454 +       const struct pio_desc usrpb[] = {
 455 +               {"USRPB", AT91C_PIN_PB(10), 0, PIO_PULLUP, PIO_INPUT},
 456 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 457 +       };
 458 +
 459 +       /* Configure the PIO controller */
 460 +       writel((1 << AT91C_ID_PIOB), PMC_PCER + AT91C_BASE_PMC);
 461 +       pio_setup(usrpb);
 462 +
 463 +       /* If USR PB is pressed during Boot sequence */
 464 +       /* Erase NandFlash block 0*/
 465 +       if ( !pio_get_value(AT91C_PIN_PB(10)) )
 466 +               df_page_erase(pDf, 0);
 467 +#endif
 468 +}
 469 +
 470 +/*------------------------------------------------------------------------------*/
 471 +/* \fn    df_hw_init                                                           */
 472 +/* \brief This function performs DataFlash HW initialization                   */
 473 +/*------------------------------------------------------------------------------*/
 474 +void df_hw_init(void)
 475 +{
 476 +       /* Configure PIOs */
 477 +       const struct pio_desc df_pio[] = {
 478 +               {"MISO",  AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
 479 +               {"MOSI",  AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
 480 +               {"SPCK",  AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
 481 +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
 482 +               {"NPCS0", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
 483 +#endif
 484 +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
 485 +               {"NPCS1", AT91C_PIN_PC(11), 0, PIO_DEFAULT, PIO_PERIPH_B},
 486 +#endif
 487 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 488 +       };
 489 +
 490 +       /* Configure the PIO controller */
 491 +       pio_setup(df_pio);
 492 +}
 493 +#endif /* CFG_DATAFLASH */
 494 +
 495 +
 496 +
 497 +#ifdef CFG_NANDFLASH
 498 +/*------------------------------------------------------------------------------*/
 499 +/* \fn    nand_recovery                                                */
 500 +/* \brief This function erases NandFlash Block 0 if USER PB is pressed                 */
 501 +/*        during boot sequence                                                 */
 502 +/*------------------------------------------------------------------------------*/
 503 +#ifdef CFG_NANDFLASH_RECOVERY
 504 +static void nand_recovery(void)
 505 +{
 506 +       /* Configure PIOs */
 507 +       const struct pio_desc usrpb[] = {
 508 +               {"USRPB", AT91C_PIN_PB(10), 0, PIO_PULLUP, PIO_INPUT},
 509 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 510 +       };
 511 +
 512 +       /* Configure the PIO controller */
 513 +       writel((1 << AT91C_ID_PIOB), PMC_PCER + AT91C_BASE_PMC);
 514 +       pio_setup(usrpb);
 515 +
 516 +       /* If USER PB is pressed during Boot sequence */
 517 +       /* Erase NandFlash block 0*/
 518 +       if (!pio_get_value(AT91C_PIN_PB(10)) )
 519 +               AT91F_NandEraseBlock0();
 520 +}
 521 +#else
 522 +static void nand_recovery(void) {}
 523 +#endif
 524 +/*------------------------------------------------------------------------------*/
 525 +/* \fn    nandflash_hw_init                                                    */
 526 +/* \brief NandFlash HW init                                                    */
 527 +/*------------------------------------------------------------------------------*/
 528 +void nandflash_hw_init(void)
 529 +{
 530 +       /* Configure PIOs */
 531 +       const struct pio_desc nand_pio[] = {
 532 +               {"RDY_BSY", AT91C_PIN_PC(13), 0, PIO_PULLUP, PIO_INPUT},
 533 +               {"NANDCS",  AT91C_PIN_PC(14), 0, PIO_PULLUP, PIO_OUTPUT},
 534 +               {(char *) 0, 0, 0,  PIO_DEFAULT, PIO_PERIPH_A},
 535 +       };
 536 +
 537 +       /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
 538 +       writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA);
 539 +
 540 +       /* Configure SMC CS3 */
 541 +       writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
 542 +       writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
 543 +       writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE)                                                , AT91C_BASE_SMC + SMC_CYCLE3);
 544 +       writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE |
 545 +               AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | AT91C_SM_TDF)                                                , AT91C_BASE_SMC + SMC_CTRL3);
 546 +
 547 +       /* Configure the PIO controller */
 548 +       writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
 549 +       pio_setup(nand_pio);
 550 +
 551 +       nand_recovery();
 552 +}
 553 +
 554 +/*------------------------------------------------------------------------------*/
 555 +/* \fn    nandflash_cfg_16bits_dbw_init                                                */
 556 +/* \brief Configure SMC in 16 bits mode                                                */
 557 +/*------------------------------------------------------------------------------*/
 558 +void nandflash_cfg_16bits_dbw_init(void)
 559 +{
 560 +       writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC + SMC_CTRL3);
 561 +}
 562 +
 563 +/*------------------------------------------------------------------------------*/
 564 +/* \fn    nandflash_cfg_8bits_dbw_init                                         */
 565 +/* \brief Configure SMC in 8 bits mode                                         */
 566 +/*------------------------------------------------------------------------------*/
 567 +void nandflash_cfg_8bits_dbw_init(void)
 568 +{
 569 +       writel((readl(AT91C_BASE_SMC + SMC_CTRL3) & ~(AT91C_SMC_DBW)) | AT91C_SMC_DBW_WIDTH_EIGTH_BITS, AT91C_BASE_SMC + SMC_CTRL3);
 570 +}
 571 +
 572 +#endif /* #ifdef CFG_NANDFLASH */
 573 diff --git a/crt0_gnu.S b/crt0_gnu.S
 574 index 042b617..002feef 100644
 575 --- a/crt0_gnu.S
 576 +++ b/crt0_gnu.S
 577 @@ -106,6 +106,13 @@ _relocate_to_sram:
 578  #endif /* CFG_NORFLASH */
 579
 580  _setup_clocks:
 581 +/* Test if main osc is bypassed */
 582 +       ldr     r0,=AT91C_PMC_MOR
 583 +       ldr     r1, [r0]
 584 +       ldr     r2,=AT91C_CKGR_OSCBYPASS
 585 +       ands    r1, r1, r2
 586 +       bne     _init_data      /* branch if OSCBYPASS=1 */
 587 +
 588  /* Test if main oscillator is enabled */
 589         ldr     r0,=AT91C_PMC_SR
 590         ldr     r1, [r0]
 591 diff --git a/include/part.h b/include/part.h
 592 index ba5985a..1d7392a 100644
 593 --- a/include/part.h
 594 +++ b/include/part.h
 595 @@ -46,7 +46,11 @@
 596
 597  #ifdef AT91SAM9G20
 598  #include "AT91SAM9260_inc.h"
 599 -#include "at91sam9g20ek.h"
 600 +       #ifdef at91sam9g20ek
 601 +       #include "at91sam9g20ek.h"
 602 +       #elif usb_a9g20_lpw
 603 +       #include "usb-a9g20-lpw.h"
 604 +       #endif
 605  #endif
 606
 607  #ifdef AT91SAM9261
 608 --
 609 1.5.6.3
 610