cirros-testvm/src-cirros/buildroot-2015.05/board/calao/tny-a9g20-lpw/at91bootstrap-1.16-tny-a9g20-lpw.patch

   1 From 53bd82b122f4530a98cba45795832820bb1d0b45 Mon Sep 17 00:00:00 2001
   2 From: Gregory Hermant <gregory.hermant@calao-systems.com>
   3 Date: Mon, 13 Aug 2012 11:26:10 +0200
   4 Subject: [PATCH] Add support for the Calao-systems TNY-A9G20-LPW
   5
   6
   7 Signed-off-by: Gregory Hermant <gregory.hermant@calao-systems.com>
   8 ---
   9  board/tny_a9g20_lpw/nandflash/Makefile        |  121 ++++++++++++
  10  board/tny_a9g20_lpw/nandflash/tny-a9g20-lpw.h |  114 ++++++++++++
  11  board/tny_a9g20_lpw/tny_a9g20_lpw.c           |  243 +++++++++++++++++++++++++
  12  crt0_gnu.S                                    |    6 +
  13  include/part.h                                |    6 +-
  14  5 files changed, 489 insertions(+), 1 deletion(-)
  15  create mode 100644 board/tny_a9g20_lpw/nandflash/Makefile
  16  create mode 100644 board/tny_a9g20_lpw/nandflash/tny-a9g20-lpw.h
  17  create mode 100644 board/tny_a9g20_lpw/tny_a9g20_lpw.c
  18
  19 diff --git a/board/tny_a9g20_lpw/nandflash/Makefile b/board/tny_a9g20_lpw/nandflash/Makefile
  20 new file mode 100644
  21 index 0000000..7efbea7
  22 --- /dev/null
  23 +++ b/board/tny_a9g20_lpw/nandflash/Makefile
  24 @@ -0,0 +1,121 @@
  25 +# TODO: set this appropriately for your local toolchain
  26 +ifndef ERASE_FCT
  27 +ERASE_FCT=rm -f
  28 +endif
  29 +ifndef CROSS_COMPILE
  30 +CROSS_COMPILE=arm-elf-
  31 +endif
  32 +
  33 +TOOLCHAIN=gcc
  34 +
  35 +BOOTSTRAP_PATH=../../..
  36 +
  37 +# NandFlashBoot Configuration for AT91SAM9260EK
  38 +
  39 +# Target name (case sensitive!!!)
  40 +TARGET=AT91SAM9G20
  41 +# Board name (case sensitive!!!)
  42 +BOARD=tny_a9g20_lpw
  43 +# Link Address and Top_of_Memory
  44 +LINK_ADDR=0x200000
  45 +TOP_OF_MEMORY=0x301000
  46 +# Name of current directory
  47 +PROJECT=nandflash
  48 +
  49 +ifndef BOOT_NAME
  50 +BOOT_NAME=$(PROJECT)_$(BOARD)
  51 +endif
  52 +
  53 +INCL=./$(BOOTSTRAP_PATH)/board/$(BOARD)/$(PROJECT)
  54 +
  55 +ifeq ($(TOOLCHAIN), gcc)
  56 +
  57 +AS=$(CROSS_COMPILE)gcc
  58 +CC=$(CROSS_COMPILE)gcc
  59 +LD=$(CROSS_COMPILE)gcc
  60 +NM= $(CROSS_COMPILE)nm
  61 +SIZE=$(CROSS_COMPILE)size
  62 +OBJCOPY=$(CROSS_COMPILE)objcopy
  63 +OBJDUMP=$(CROSS_COMPILE)objdump
  64 +CCFLAGS=-g -mcpu=arm926ej-s -Os -Wall -D$(TARGET) -D$(BOARD) -I$(INCL)
  65 +ASFLAGS=-g -mcpu=arm926ej-s -c -Os -Wall -D$(TARGET) -D$(BOARD) -I$(INCL) -DTOP_OF_MEM=$(TOP_OF_MEMORY)
  66 +
  67 +# Linker flags.
  68 +#  -Wl,...:     tell GCC to pass this to linker.
  69 +#    -Map:      create map file
  70 +#    --cref:    add cross reference to map file
  71 +LDFLAGS+=-nostartfiles -nostdlib -Wl,-Map=$(BOOT_NAME).map,--cref
  72 +LDFLAGS+=-T $(BOOTSTRAP_PATH)/elf32-littlearm.lds -Ttext $(LINK_ADDR)
  73 +OBJS=crt0_gnu.o
  74 +
  75 +endif
  76 +
  77 +OBJS+=\
  78 +       $(BOARD).o \
  79 +       main.o \
  80 +       gpio.o \
  81 +       pmc.o \
  82 +       debug.o \
  83 +       sdramc.o \
  84 +       nandflash.o \
  85 +       _udivsi3.o \
  86 +       _umodsi3.o \
  87 +       div0.o \
  88 +       udiv.o \
  89 +       string.o
  90 +
  91 +rebuild: clean all
  92 +
  93 +all:   $(BOOT_NAME)
  94 +
  95 +ifeq ($(TOOLCHAIN), gcc)
  96 +$(BOOT_NAME): $(OBJS)
  97 +       $(LD) $(LDFLAGS) -n -o $(BOOT_NAME).elf $(OBJS)
  98 +       $(OBJCOPY) --strip-debug --strip-unneeded $(BOOT_NAME).elf -O binary $(BOOT_NAME).bin
  99 +endif
 100 +
 101 +
 102 +$(BOARD).o: $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c
 103 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c -o $(BOARD).o
 104 +
 105 +main.o: $(BOOTSTRAP_PATH)/main.c
 106 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/main.c -o main.o
 107 +
 108 +gpio.o: $(BOOTSTRAP_PATH)/driver/gpio.c
 109 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/gpio.c -o gpio.o
 110 +
 111 +pmc.o:  $(BOOTSTRAP_PATH)/driver/pmc.c
 112 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/pmc.c -o pmc.o
 113 +
 114 +debug.o: $(BOOTSTRAP_PATH)/driver/debug.c
 115 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/debug.c -o debug.o
 116 +
 117 +sdramc.o:  $(BOOTSTRAP_PATH)/driver/sdramc.c
 118 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/sdramc.c -o sdramc.o
 119 +
 120 +dataflash.o:  $(BOOTSTRAP_PATH)/driver/dataflash.c
 121 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/dataflash.c -o dataflash.o
 122 +
 123 +nandflash.o:  $(BOOTSTRAP_PATH)/driver/nandflash.c
 124 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/nandflash.c -o nandflash.o
 125 +
 126 +crt0_gnu.o:  $(BOOTSTRAP_PATH)/crt0_gnu.S
 127 +       $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/crt0_gnu.S -o crt0_gnu.o
 128 +
 129 +div0.o:  $(BOOTSTRAP_PATH)/lib/div0.c
 130 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/div0.c -o div0.o
 131 +
 132 +string.o:  $(BOOTSTRAP_PATH)/lib/string.c
 133 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/string.c -o string.o
 134 +
 135 +udiv.o:  $(BOOTSTRAP_PATH)/lib/udiv.c
 136 +       $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/udiv.c -o udiv.o
 137 +
 138 +_udivsi3.o:  $(BOOTSTRAP_PATH)/lib/_udivsi3.S
 139 +       $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_udivsi3.S -o _udivsi3.o
 140 +
 141 +_umodsi3.o:  $(BOOTSTRAP_PATH)/lib/_umodsi3.S
 142 +       $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_umodsi3.S -o _umodsi3.o
 143 +
 144 +clean:
 145 +       $(ERASE_FCT) *.o *.bin *.elf *.map
 146 diff --git a/board/tny_a9g20_lpw/nandflash/tny-a9g20-lpw.h b/board/tny_a9g20_lpw/nandflash/tny-a9g20-lpw.h
 147 new file mode 100644
 148 index 0000000..b1f8a1d
 149 --- /dev/null
 150 +++ b/board/tny_a9g20_lpw/nandflash/tny-a9g20-lpw.h
 151 @@ -0,0 +1,114 @@
 152 +/* ----------------------------------------------------------------------------
 153 + *         ATMEL Microcontroller Software Support  -  ROUSSET  -
 154 + * ----------------------------------------------------------------------------
 155 + * Copyright (c) 2008, Atmel Corporation
 156 +
 157 + * All rights reserved.
 158 + *
 159 + * Redistribution and use in source and binary forms, with or without
 160 + * modification, are permitted provided that the following conditions are met:
 161 + *
 162 + * - Redistributions of source code must retain the above copyright notice,
 163 + * this list of conditions and the disclaimer below.
 164 + *
 165 + * Atmel's name may not be used to endorse or promote products derived from
 166 + * this software without specific prior written permission.
 167 + *
 168 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 169 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 170 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 171 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 172 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 173 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 174 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 175 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 176 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 177 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 178 + * ----------------------------------------------------------------------------
 179 + * File Name           : tny-a9g20-lpw.h
 180 + * Object              :
 181 + * Creation            : GH August 13th 2012
 182 + *-----------------------------------------------------------------------------
 183 + */
 184 +#ifndef _TNY_A9G20_LPW_H
 185 +#define _TNY_A9G20_LPW_H
 186 +
 187 +/* ******************************************************************* */
 188 +/* PMC Settings                                                        */
 189 +/*                                                                     */
 190 +/* The main oscillator is enabled as soon as possible in the c_startup */
 191 +/* and MCK is switched on the main oscillator.                         */
 192 +/* PLL initialization is done later in the hw_init() function          */
 193 +/* ******************************************************************* */
 194 +#define MASTER_CLOCK           (100000000)
 195 +#define PLL_LOCK_TIMEOUT       1000000
 196 +
 197 +/* set PLLA to 800Mhz from MAINCK= 12Mhz MULA=199 (0xC7+1= 200), DIVA=0x03 (Fplla=12Mhz x [(199+1)/3]=800Mhz) */
 198 +#define PLLA_SETTINGS   0x20C73F03
 199 +#define PLLB_SETTINGS   0x100F3F02
 200 +
 201 +/* Switch MCK on PLLA output PCK = PLLA/2 = 3 * MCK */
 202 +/* LP-SDRAM (fmax=100Mhz) PDIV=0 => PRESCALER CLK=PCLK; */
 203 +/* MDIV = 2 => PRESCALER CLK / 4 = MCLK=100Mhz */
 204 +/* PRESCALER CLK = PLLA (800Mhz) / 2 (PRES=1) = 400Mhz */
 205 +#define MCKR_SETTINGS           0x0204
 206 +#define MCKR_CSS_SETTINGS       (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS)
 207 +
 208 +/* ******************************************************************* */
 209 +/* NandFlash Settings                                                  */
 210 +/*                                                                     */
 211 +/* ******************************************************************* */
 212 +#define AT91C_SMARTMEDIA_BASE  0x40000000
 213 +
 214 +#define AT91_SMART_MEDIA_ALE    (1 << 21)      /* our ALE is AD21 */
 215 +#define AT91_SMART_MEDIA_CLE    (1 << 22)      /* our CLE is AD22 */
 216 +
 217 +#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
 218 +#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
 219 +
 220 +#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
 221 +
 222 +
 223 +/* ******************************************************************** */
 224 +/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
 225 +/* Please refer to SMC section in AT91SAM9 datasheet to learn how      */
 226 +/* to generate these values.                                           */
 227 +/* ******************************************************************** */
 228 +#define AT91C_SM_NWE_SETUP     (1 << 0)
 229 +#define AT91C_SM_NCS_WR_SETUP  (0 << 8)
 230 +#define AT91C_SM_NRD_SETUP     (1 << 16)
 231 +#define AT91C_SM_NCS_RD_SETUP  (0 << 24)
 232 +
 233 +#define AT91C_SM_NWE_PULSE     (3 << 0)
 234 +#define AT91C_SM_NCS_WR_PULSE  (3 << 8)
 235 +#define AT91C_SM_NRD_PULSE     (3 << 16)
 236 +#define AT91C_SM_NCS_RD_PULSE  (3 << 24)
 237 +
 238 +#define AT91C_SM_NWE_CYCLE     (5 << 0)
 239 +#define AT91C_SM_NRD_CYCLE     (5 << 16)
 240 +
 241 +#define AT91C_SM_TDF           (2 << 16)
 242 +
 243 +/* ******************************************************************* */
 244 +/* BootStrap Settings                                                  */
 245 +/*                                                                     */
 246 +/* ******************************************************************* */
 247 +#define IMG_ADDRESS            0x20000                 /* Image Address in NandFlash */
 248 +#define        IMG_SIZE                0x40000                 /* Image Size in NandFlash */
 249 +
 250 +#define MACH_TYPE              0x80B                   /* TNY-A9G20 */
 251 +#define JUMP_ADDR              0x23F00000              /* Final Jump Address */
 252 +
 253 +/* ******************************************************************* */
 254 +/* Application Settings                                                */
 255 +/* ******************************************************************* */
 256 +#undef CFG_DEBUG
 257 +#undef CFG_DATAFLASH
 258 +
 259 +#define CFG_NANDFLASH
 260 +#undef NANDFLASH_SMALL_BLOCKS  /* NANDFLASH_LARGE_BLOCKS used instead */
 261 +
 262 +#define        CFG_SDRAM
 263 +#define        CFG_HW_INIT
 264 +
 265 +#endif /* _TNY_A9G20_LPW_H */
 266 diff --git a/board/tny_a9g20_lpw/tny_a9g20_lpw.c b/board/tny_a9g20_lpw/tny_a9g20_lpw.c
 267 new file mode 100644
 268 index 0000000..cef9055
 269 --- /dev/null
 270 +++ b/board/tny_a9g20_lpw/tny_a9g20_lpw.c
 271 @@ -0,0 +1,243 @@
 272 +/* ----------------------------------------------------------------------------
 273 + *         ATMEL Microcontroller Software Support  -  ROUSSET  -
 274 + * ----------------------------------------------------------------------------
 275 + * Copyright (c) 2008, Atmel Corporation
 276 +
 277 + * All rights reserved.
 278 + *
 279 + * Redistribution and use in source and binary forms, with or without
 280 + * modification, are permitted provided that the following conditions are met:
 281 + *
 282 + * - Redistributions of source code must retain the above copyright notice,
 283 + * this list of conditions and the disclaimer below.
 284 + *
 285 + * Atmel's name may not be used to endorse or promote products derived from
 286 + * this software without specific prior written permission.
 287 + *
 288 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 289 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 290 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 291 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 292 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 293 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 294 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 295 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 296 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 297 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 298 + * ----------------------------------------------------------------------------
 299 + * File Name           : tny_a9g20_lpw.c
 300 + * Object              :
 301 + * Creation            : GH August 13th 2012
 302 + *-----------------------------------------------------------------------------
 303 + */
 304 +#include "../../include/part.h"
 305 +#include "../../include/gpio.h"
 306 +#include "../../include/pmc.h"
 307 +#include "../../include/debug.h"
 308 +#include "../../include/sdramc.h"
 309 +#include "../../include/main.h"
 310 +#ifdef CFG_NANDFLASH
 311 +#include "../../include/nandflash.h"
 312 +#endif
 313 +
 314 +static inline unsigned int get_cp15(void)
 315 +{
 316 +       unsigned int value;
 317 +       __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value));
 318 +       return value;
 319 +}
 320 +
 321 +static inline void set_cp15(unsigned int value)
 322 +{
 323 +       __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value));
 324 +}
 325 +
 326 +#ifdef CFG_HW_INIT
 327 +/*----------------------------------------------------------------------------*/
 328 +/* \fn    hw_init                                                            */
 329 +/* \brief This function performs very low level HW initialization            */
 330 +/* This function is invoked as soon as possible during the c_startup         */
 331 +/* The bss segment must be initialized                                       */
 332 +/*----------------------------------------------------------------------------*/
 333 +void hw_init(void)
 334 +{
 335 +       unsigned int cp15;
 336 +
 337 +       /* Configure PIOs */
 338 +       const struct pio_desc hw_pio[] = {
 339 +#ifdef CFG_DEBUG
 340 +               {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
 341 +               {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
 342 +#endif
 343 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 344 +       };
 345 +
 346 +       /* Disable watchdog */
 347 +       writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
 348 +
 349 +       /* At this stage the main oscillator is supposed to be enabled
 350 +        * PCK = MCK = MOSC */
 351 +       writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);
 352 +
 353 +       /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
 354 +       pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
 355 +
 356 +       /* PCK = PLLA/2 = 3 * MCK */
 357 +       pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
 358 +       /* Switch MCK on PLLA output */
 359 +       pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
 360 +
 361 +       /* Configure PLLB */
 362 +       pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
 363 +
 364 +       /* Configure CP15 */
 365 +       cp15 = get_cp15();
 366 +       cp15 |= I_CACHE;
 367 +       set_cp15(cp15);
 368 +
 369 +       /* Configure the PIO controller */
 370 +       pio_setup(hw_pio);
 371 +
 372 +       /* Configure the EBI Slave Slot Cycle to 64 */
 373 +       writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3));
 374 +
 375 +#ifdef CFG_DEBUG
 376 +       /* Enable Debug messages on the DBGU */
 377 +       dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
 378 +
 379 +       dbg_print("Start AT91Bootstrap...\n\r");
 380 +#endif /* CFG_DEBUG */
 381 +
 382 +#ifdef CFG_SDRAM
 383 +       /* Initialize the matrix (slow slew rate enabled and LPSDRAM memory voltage = 1.8V) */
 384 +       writel(((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC | (1<<17)) & ~0x00010000, AT91C_BASE_CCFG + CCFG_EBICSA);
 385 +
 386 +       /* Configure SDRAM Controller */
 387 +       sdram_init(     AT91C_SDRAMC_NC_9  |
 388 +                               AT91C_SDRAMC_NR_13 |
 389 +                               AT91C_SDRAMC_CAS_3 |
 390 +                               AT91C_SDRAMC_NB_4_BANKS |
 391 +                               AT91C_SDRAMC_DBW_32_BITS |
 392 +                               AT91C_SDRAMC_TWR_2 |
 393 +                               AT91C_SDRAMC_TRC_7 |
 394 +                               AT91C_SDRAMC_TRP_2 |
 395 +                               AT91C_SDRAMC_TRCD_2 |
 396 +                               AT91C_SDRAMC_TRAS_5 |
 397 +                               AT91C_SDRAMC_TXSR_8,            /* Control Register */
 398 +                               (MASTER_CLOCK * 7)/1000000,     /* Refresh Timer Register */
 399 +                                AT91C_SDRAMC_MD_LOW_POWER_SDRAM); /* SDRAM (low power)   */
 400 +
 401 +#endif /* CFG_SDRAM */
 402 +}
 403 +#endif /* CFG_HW_INIT */
 404 +
 405 +#ifdef CFG_SDRAM
 406 +/*------------------------------------------------------------------------------*/
 407 +/* \fn    sdramc_hw_init                                                       */
 408 +/* \brief This function performs SDRAMC HW initialization                      */
 409 +/*------------------------------------------------------------------------------*/
 410 +void sdramc_hw_init(void)
 411 +{
 412 +       /* Configure PIOs */
 413 +/*     const struct pio_desc sdramc_pio[] = {
 414 +               {"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
 415 +               {"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
 416 +               {"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
 417 +               {"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
 418 +               {"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
 419 +               {"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
 420 +               {"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
 421 +               {"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
 422 +               {"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
 423 +               {"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
 424 +               {"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
 425 +               {"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
 426 +               {"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
 427 +               {"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
 428 +               {"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
 429 +               {"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
 430 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 431 +       };
 432 +*/
 433 +       /* Configure the SDRAMC PIO controller to output PCK0 */
 434 +/*     pio_setup(sdramc_pio); */
 435 +
 436 +       writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
 437 +       writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
 438 +
 439 +}
 440 +#endif /* CFG_SDRAM */
 441 +
 442 +#ifdef CFG_NANDFLASH
 443 +/*------------------------------------------------------------------------------*/
 444 +/* \fn    nand_recovery                                                */
 445 +/* \brief This function erases NandFlash Block 0 if BP4 is pressed             */
 446 +/*        during boot sequence                                                 */
 447 +/*------------------------------------------------------------------------------*/
 448 +static void nand_recovery(void)
 449 +{
 450 +       /* Configure PIOs */
 451 +       const struct pio_desc bp4_pio[] = {
 452 +               {"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
 453 +               {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
 454 +       };
 455 +
 456 +       /* Configure the PIO controller */
 457 +       writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
 458 +       pio_setup(bp4_pio);
 459 +
 460 +       /* If BP4 is pressed during Boot sequence */
 461 +       /* Erase NandFlash block 0*/
 462 +       if (!pio_get_value(AT91C_PIN_PA(31)) )
 463 +               AT91F_NandEraseBlock0();
 464 +}
 465 +
 466 +/*------------------------------------------------------------------------------*/
 467 +/* \fn    nandflash_hw_init                                                    */
 468 +/* \brief NandFlash HW init                                                    */
 469 +/*------------------------------------------------------------------------------*/
 470 +void nandflash_hw_init(void)
 471 +{
 472 +       /* Configure PIOs */
 473 +       const struct pio_desc nand_pio[] = {
 474 +               {"RDY_BSY", AT91C_PIN_PC(13), 0, PIO_PULLUP, PIO_INPUT},
 475 +               {"NANDCS",  AT91C_PIN_PC(14), 0, PIO_PULLUP, PIO_OUTPUT},
 476 +               {(char *) 0, 0, 0,  PIO_DEFAULT, PIO_PERIPH_A},
 477 +       };
 478 +
 479 +       /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
 480 +       writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA);
 481 +
 482 +       /* Configure SMC CS3 */
 483 +       writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
 484 +       writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
 485 +       writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE)                                                , AT91C_BASE_SMC + SMC_CYCLE3);
 486 +       writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE |
 487 +               AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | AT91C_SM_TDF)                                                , AT91C_BASE_SMC + SMC_CTRL3);
 488 +
 489 +       /* Configure the PIO controller */
 490 +       writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
 491 +       pio_setup(nand_pio);
 492 +
 493 +       nand_recovery();
 494 +}
 495 +
 496 +/*------------------------------------------------------------------------------*/
 497 +/* \fn    nandflash_cfg_16bits_dbw_init                                                */
 498 +/* \brief Configure SMC in 16 bits mode                                                */
 499 +/*------------------------------------------------------------------------------*/
 500 +void nandflash_cfg_16bits_dbw_init(void)
 501 +{
 502 +       writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC + SMC_CTRL3);
 503 +}
 504 +
 505 +/*------------------------------------------------------------------------------*/
 506 +/* \fn    nandflash_cfg_8bits_dbw_init                                         */
 507 +/* \brief Configure SMC in 8 bits mode                                         */
 508 +/*------------------------------------------------------------------------------*/
 509 +void nandflash_cfg_8bits_dbw_init(void)
 510 +{
 511 +       writel((readl(AT91C_BASE_SMC + SMC_CTRL3) & ~(AT91C_SMC_DBW)) | AT91C_SMC_DBW_WIDTH_EIGTH_BITS, AT91C_BASE_SMC + SMC_CTRL3);
 512 +}
 513 +
 514 +#endif /* #ifdef CFG_NANDFLASH */
 515 diff --git a/crt0_gnu.S b/crt0_gnu.S
 516 index 042b617..c6cd49d 100644
 517 --- a/crt0_gnu.S
 518 +++ b/crt0_gnu.S
 519 @@ -106,6 +106,12 @@ _relocate_to_sram:
 520  #endif /* CFG_NORFLASH */
 521
 522  _setup_clocks:
 523 +/* Test if main osc is bypassed */
 524 +       ldr     r0,=AT91C_PMC_MOR
 525 +       ldr     r1, [r0]
 526 +       ldr     r2,=AT91C_CKGR_OSCBYPASS
 527 +       ands    r1, r1, r2
 528 +       bne     _init_data      /* branch if OSCBYPASS=1 */
 529  /* Test if main oscillator is enabled */
 530         ldr     r0,=AT91C_PMC_SR
 531         ldr     r1, [r0]
 532 diff --git a/include/part.h b/include/part.h
 533 index ba5985a..ab79af1 100644
 534 --- a/include/part.h
 535 +++ b/include/part.h
 536 @@ -46,7 +46,11 @@
 537
 538  #ifdef AT91SAM9G20
 539  #include "AT91SAM9260_inc.h"
 540 -#include "at91sam9g20ek.h"
 541 +       #ifdef at91sam9g20ek
 542 +       #include "at91sam9g20ek.h"
 543 +       #elif tny_a9g20_lpw
 544 +       #include "tny-a9g20-lpw.h"
 545 +       #endif
 546  #endif
 547
 548  #ifdef AT91SAM9261
 549 --
 550 1.7.9.5
 551