cirros-testvm/src-cirros/buildroot-2015.05/board/altera/sockit/uboot-sockit-preloader-sample-design.patch

   1 From c70f2ebb350da20af1a0ed4b7960b8e5a1952713 Mon Sep 17 00:00:00 2001
   2 From: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
   3 Date: Thu, 20 Feb 2014 11:51:31 -0500
   4 Subject: [PATCH] board: add to sockit a working preloader design
   5
   6 ---
   7  board/altera/socfpga_cyclone5/build.h              |   2 +-
   8  board/altera/socfpga_cyclone5/iocsr_config.c       | 314 ++++++++++-----------
   9  board/altera/socfpga_cyclone5/pinmux_config.c      |  32 +--
  10  board/altera/socfpga_cyclone5/pinmux_config.h      |   8 +-
  11  board/altera/socfpga_cyclone5/sdram/sdram_config.h |  14 +-
  12  .../altera/socfpga_cyclone5/sdram/sequencer_auto.h |  16 +-
  13  .../sdram/sequencer_auto_ac_init.c                 |  16 +-
  14  .../socfpga_cyclone5/sdram/sequencer_defines.h     |  34 +--
  15  8 files changed, 218 insertions(+), 218 deletions(-)
  16
  17 diff --git a/board/altera/socfpga_cyclone5/build.h b/board/altera/socfpga_cyclone5/build.h
  18 index e5d9c3c..a369015 100644
  19 --- a/board/altera/socfpga_cyclone5/build.h
  20 +++ b/board/altera/socfpga_cyclone5/build.h
  21 @@ -29,7 +29,7 @@
  22   * Handoff files must provide user option whether to
  23   * enable watchdog during preloader execution phase
  24   */
  25 -#define CONFIG_PRELOADER_WATCHDOG_ENABLE       (0)
  26 +#define CONFIG_PRELOADER_WATCHDOG_ENABLE       (1)
  27
  28  /*
  29   * Handoff files must provide user option whether to enable
  30 diff --git a/board/altera/socfpga_cyclone5/iocsr_config.c b/board/altera/socfpga_cyclone5/iocsr_config.c
  31 index fa663e1..90fc154 100644
  32 --- a/board/altera/socfpga_cyclone5/iocsr_config.c
  33 +++ b/board/altera/socfpga_cyclone5/iocsr_config.c
  34 @@ -7,113 +7,113 @@ const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH
  35         0xC0000000,
  36         0x0000003F,
  37         0x00008000,
  38 -       0x00020080,
  39 -       0x08020000,
  40 -       0x08000000,
  41 -       0x00018020,
  42 +       0x00060180,
  43 +       0x18060000,
  44 +       0x18000000,
  45 +       0x00018060,
  46         0x00000000,
  47         0x00004000,
  48 -       0x00010040,
  49 -       0x04010000,
  50 -       0x04000000,
  51 -       0x00000010,
  52 -       0x00004010,
  53 +       0x000300C0,
  54 +       0x0C030000,
  55 +       0x0C000000,
  56 +       0x00000030,
  57 +       0x0000C030,
  58         0x00002000,
  59 -       0x00020000,
  60 -       0x02008000,
  61 -       0x02000000,
  62 -       0x00000008,
  63 -       0x00002008,
  64 +       0x00018060,
  65 +       0x06018000,
  66 +       0x06000000,
  67 +       0x00000018,
  68 +       0x00006018,
  69         0x00001000,
  70  };
  71
  72  const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
  73 -       0x000C0300,
  74 -       0x10040000,
  75 -       0x100000C0,
  76 -       0x00000040,
  77 -       0x00010040,
  78 +       0x00100000,
  79 +       0x300C0000,
  80 +       0x300000C0,
  81 +       0x000000C0,
  82 +       0x000300C0,
  83         0x00008000,
  84         0x00080000,
  85 -       0x18060000,
  86 -       0x18000000,
  87 -       0x00000060,
  88 -       0x00018060,
  89 +       0x20000000,
  90 +       0x00000000,
  91 +       0x00000080,
  92 +       0x00020000,
  93         0x00004000,
  94 -       0x00010040,
  95 +       0x000300C0,
  96         0x10000000,
  97 -       0x04000000,
  98 -       0x00000010,
  99 -       0x00004010,
 100 +       0x0C000000,
 101 +       0x00000030,
 102 +       0x0000C030,
 103         0x00002000,
 104 -       0x06008020,
 105 -       0x02008000,
 106 +       0x06018060,
 107 +       0x06018000,
 108         0x01FE0000,
 109         0xF8000000,
 110         0x00000007,
 111         0x00001000,
 112 -       0x00004010,
 113 -       0x01004000,
 114 -       0x01000000,
 115 -       0x00003004,
 116 -       0x00001004,
 117 +       0x0000C030,
 118 +       0x0300C000,
 119 +       0x03000000,
 120 +       0x0000300C,
 121 +       0x0000300C,
 122         0x00000800,
 123         0x00000000,
 124         0x00000000,
 125 -       0x00800000,
 126 -       0x00000002,
 127 +       0x01800000,
 128 +       0x00000006,
 129         0x00002000,
 130         0x00000400,
 131         0x00000000,
 132 -       0x00401000,
 133 +       0x00C03000,
 134         0x00000003,
 135         0x00000000,
 136         0x00000000,
 137         0x00000200,
 138 -       0x00600802,
 139 +       0x00601806,
 140         0x00000000,
 141 -       0x80200000,
 142 -       0x80000600,
 143 -       0x00000200,
 144 +       0x80600000,
 145 +       0x80000601,
 146 +       0x00000601,
 147         0x00000100,
 148 -       0x00300401,
 149 -       0xC0100400,
 150 -       0x40100000,
 151 -       0x40000300,
 152 -       0x000C0100,
 153 +       0x00300C03,
 154 +       0xC0300C00,
 155 +       0xC0300000,
 156 +       0xC0000300,
 157 +       0x000C0300,
 158         0x00000080,
 159  };
 160
 161  const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
 162 -       0x80040100,
 163 +       0x300C0300,
 164         0x00000000,
 165         0x0FF00000,
 166         0x00000000,
 167 -       0x0C010040,
 168 +       0x0C0300C0,
 169         0x00008000,
 170 -       0x18020080,
 171 -       0x00000000,
 172 -       0x08000000,
 173 -       0x00040020,
 174 -       0x06018060,
 175 +       0x18060180,
 176 +       0x18060000,
 177 +       0x18000000,
 178 +       0x00018060,
 179 +       0x00018060,
 180         0x00004000,
 181 -       0x0C010040,
 182 -       0x04010000,
 183 +       0x000300C0,
 184 +       0x0C030000,
 185         0x00000030,
 186         0x00000000,
 187 -       0x03004010,
 188 +       0x0300C030,
 189         0x00002000,
 190 -       0x06008020,
 191 -       0x02008000,
 192 -       0x02000018,
 193 -       0x00006008,
 194 -       0x01802008,
 195 +       0x00018060,
 196 +       0x06018000,
 197 +       0x06000000,
 198 +       0x00000018,
 199 +       0x00006018,
 200         0x00001000,
 201 -       0x03004010,
 202 -       0x01004000,
 203 -       0x0100000C,
 204 -       0x00003004,
 205 -       0x00C01004,
 206 +       0x0000C030,
 207 +       0x00000000,
 208 +       0x03000000,
 209 +       0x0000000C,
 210 +       0x00C0300C,
 211         0x00000800,
 212  };
 213
 214 @@ -170,14 +170,14 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 215         0xA0000034,
 216         0x0D000001,
 217         0x6068030C,
 218 -       0xC7034018,
 219 -       0x0E381A01,
 220 +       0xCF034059,
 221 +       0x1E781A03,
 222         0x8030C0D0,
 223 -       0x34018606,
 224 -       0x01A01C70,
 225 +       0x34059606,
 226 +       0x01A03CF0,
 227         0x0C0D0000,
 228 -       0x18606803,
 229 -       0x01C70340,
 230 +       0x59606803,
 231 +       0x03CF0340,
 232         0xD000001A,
 233         0x068030C0,
 234         0x10040000,
 235 @@ -244,15 +244,15 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 236         0xA0000034,
 237         0x0D000001,
 238         0x6068030C,
 239 -       0xC7034018,
 240 -       0x0E381A01,
 241 +       0xCF034059,
 242 +       0x1E781A03,
 243         0x8030C0D0,
 244 -       0x34018606,
 245 +       0x34059606,
 246         0x01A00000,
 247         0x0C0D0000,
 248 -       0x18606803,
 249 -       0x01C70340,
 250 -       0xD00E381A,
 251 +       0x59606803,
 252 +       0x03CF0340,
 253 +       0xD01E781A,
 254         0x068030C0,
 255         0x10040000,
 256         0x00200000,
 257 @@ -273,7 +273,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 258         0xAA0D4000,
 259         0x01C3A810,
 260         0xAA0D4000,
 261 -       0x01C3A808,
 262 +       0x01C3A810,
 263         0xAA0D4000,
 264         0x01C3A810,
 265         0x00040100,
 266 @@ -301,7 +301,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 267         0x2A835000,
 268         0x0070EA04,
 269         0x2A835000,
 270 -       0x0070EA02,
 271 +       0x0070EA04,
 272         0x2A835000,
 273         0x0070EA04,
 274         0x00010040,
 275 @@ -321,15 +321,15 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 276         0x14864000,
 277         0x69A47A05,
 278         0xCBCF23D7,
 279 -       0xF41E791E,
 280 -       0x034ED348,
 281 +       0xF5DE791E,
 282 +       0x0356D348,
 283         0x821A0000,
 284         0x0000D000,
 285         0x01860680,
 286         0xD769A47A,
 287         0x1ECBCF23,
 288 -       0x48F41E79,
 289 -       0x00034ED3,
 290 +       0x48F5DE79,
 291 +       0x000356D3,
 292         0x00080200,
 293         0x00001000,
 294         0x00080200,
 295 @@ -347,7 +347,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 296         0xAA0D4000,
 297         0x01C3A810,
 298         0xAA0D4000,
 299 -       0x01C3A808,
 300 +       0x01C3A810,
 301         0xAA0D4000,
 302         0x01C3A810,
 303         0x00040100,
 304 @@ -375,7 +375,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 305         0x2A835000,
 306         0x0070EA04,
 307         0x2A835000,
 308 -       0x0070EA02,
 309 +       0x0070EA04,
 310         0x2A835000,
 311         0x0070EA04,
 312         0x00015000,
 313 @@ -395,15 +395,15 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 314         0x14864000,
 315         0x69A47A05,
 316         0xCBCF23D7,
 317 -       0xF41E791E,
 318 -       0x034ED348,
 319 -       0x821A00C3,
 320 +       0xF5DE791E,
 321 +       0x0356D348,
 322 +       0x821A02CB,
 323         0x0000D000,
 324         0x00000680,
 325         0xD769A47A,
 326         0x1ECBCF23,
 327 -       0x48F41E79,
 328 -       0x00034ED3,
 329 +       0x48F5DE79,
 330 +       0x000356D3,
 331         0x00080200,
 332         0x00001000,
 333         0x00080200,
 334 @@ -421,7 +421,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 335         0xAA0D4000,
 336         0x01C3A810,
 337         0xAA0D4000,
 338 -       0x01C3A808,
 339 +       0x01C3A810,
 340         0xAA0D4000,
 341         0x01C3A810,
 342         0x00040100,
 343 @@ -449,7 +449,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 344         0x2A835000,
 345         0x0070EA04,
 346         0x2A835000,
 347 -       0x0070EA02,
 348 +       0x0070EA04,
 349         0x2A835000,
 350         0x0070EA04,
 351         0x00010040,
 352 @@ -469,15 +469,15 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 353         0x14864000,
 354         0x69A47A05,
 355         0xCBCF23D7,
 356 -       0xF41E791E,
 357 -       0x034ED348,
 358 +       0xF5DE791E,
 359 +       0x0356D348,
 360         0x821A0000,
 361         0x0000D000,
 362         0x00000680,
 363         0xD769A47A,
 364         0x1ECBCF23,
 365 -       0x48F41E79,
 366 -       0x00034ED3,
 367 +       0x48F5DE79,
 368 +       0x000356D3,
 369         0x00080200,
 370         0x00001000,
 371         0x00080200,
 372 @@ -495,7 +495,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 373         0xAA0D4000,
 374         0x01C3A810,
 375         0xAA0D4000,
 376 -       0x01C3A808,
 377 +       0x01C3A810,
 378         0xAA0D4000,
 379         0x01C3A810,
 380         0x00040100,
 381 @@ -523,7 +523,7 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 382         0x2A835000,
 383         0x0070EA04,
 384         0x2A835000,
 385 -       0x0070EA02,
 386 +       0x0070EA04,
 387         0x2A835000,
 388         0x0070EA04,
 389         0x00010040,
 390 @@ -543,15 +543,15 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 391         0x14864000,
 392         0x69A47A05,
 393         0xCBCF23D7,
 394 -       0xF41E791E,
 395 -       0x034ED348,
 396 +       0xF5DE791E,
 397 +       0x0356D348,
 398         0x821A0000,
 399         0x0000D000,
 400         0x00000680,
 401         0xD769A47A,
 402         0x1ECBCF23,
 403 -       0x48F41E79,
 404 -       0x00034ED3,
 405 +       0x48F5DE79,
 406 +       0x000356D3,
 407         0x00080200,
 408         0x00001000,
 409         0x00080200,
 410 @@ -567,80 +567,80 @@ const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH
 411         0x04000002,
 412         0x00820000,
 413         0x00489000,
 414 -       0x001A1A1A,
 415 -       0x085506A0,
 416 -       0x0000E1D4,
 417 -       0x045506A0,
 418 -       0x0000E1D4,
 419 -       0x085506A0,
 420 -       0x8000E1D4,
 421 +       0x801A1A1A,
 422 +       0x00000200,
 423 +       0x80000004,
 424 +       0x00000200,
 425 +       0x80000004,
 426 +       0x00000200,
 427 +       0x80000004,
 428         0x00000200,
 429         0x00000004,
 430 -       0x04000000,
 431 -       0x00000009,
 432 -       0x00002410,
 433 +       0x00040000,
 434 +       0x10000000,
 435 +       0x00000000,
 436         0x00000040,
 437 -       0x41000000,
 438 -       0x00002082,
 439 -       0x00000350,
 440 -       0x000000DA,
 441 +       0x00010000,
 442 +       0x40002000,
 443 +       0x00000100,
 444 +       0x40000002,
 445 +       0x00000100,
 446 +       0x40000002,
 447         0x00000100,
 448         0x40000002,
 449         0x00000100,
 450         0x00000002,
 451 -       0x042A8350,
 452 -       0x000070EA,
 453 -       0x86000000,
 454 -       0x08000004,
 455 +       0x00020000,
 456 +       0x08000000,
 457         0x00000000,
 458 -       0x00482000,
 459 -       0x21800000,
 460 -       0x00101061,
 461 -       0x021541A8,
 462 -       0x00003875,
 463 -       0x011541A8,
 464 -       0x00003875,
 465 -       0x021541A8,
 466 -       0x20003875,
 467 +       0x00000020,
 468 +       0x00008000,
 469 +       0x20001000,
 470 +       0x00000080,
 471 +       0x20000001,
 472 +       0x00000080,
 473 +       0x20000001,
 474 +       0x00000080,
 475 +       0x20000001,
 476         0x00000080,
 477         0x00000001,
 478 -       0x41000000,
 479 -       0x00000002,
 480 -       0x00FF0904,
 481 +       0x00010000,
 482 +       0x04000000,
 483 +       0x00FF0000,
 484         0x00000000,
 485 -       0x90400000,
 486 -       0x00000820,
 487 +       0x00004000,
 488 +       0x00000800,
 489         0x80000001,
 490 -       0x38D612AF,
 491 -       0x86F8E38E,
 492 -       0x0A0A78B4,
 493 -       0x000D020A,
 494 +       0x00041419,
 495 +       0x40000000,
 496 +       0x04000816,
 497 +       0x000D0000,
 498         0x00006800,
 499 -       0x028A4320,
 500 -       0xEBB4D23D,
 501 -       0x8F65E791,
 502 -       0xA47A0F3C,
 503 -       0x0001A769,
 504 -       0x00410D00,
 505 +       0x00000340,
 506 +       0xD000001A,
 507 +       0x06800000,
 508 +       0x00340000,
 509 +       0x0001A000,
 510 +       0x00000D00,
 511         0x40000068,
 512 -       0x3D000003,
 513 -       0x91EBB4D2,
 514 -       0x3C8F65E7,
 515 -       0x69A47A0F,
 516 -       0x000001A7,
 517 +       0x1A000003,
 518 +       0x00D00000,
 519 +       0x00068000,
 520 +       0x00003400,
 521 +       0x000001A0,
 522 +       0x00000401,
 523 +       0x00000008,
 524         0x00000401,
 525         0x00000008,
 526         0x00000401,
 527         0x00000008,
 528 -       0x00000540,
 529 -       0x000003A8,
 530 -       0x10AA0D40,
 531 -       0x8001C3A8,
 532 +       0x00000401,
 533 +       0x80000008,
 534         0x0000007F,
 535 +       0x20000000,
 536         0x00000000,
 537 -       0x00004060,
 538 -       0xE1208000,
 539 +       0xE0000080,
 540         0x0000001F,
 541 -       0x00004100,
 542 +       0x00004000,
 543  };
 544
 545 diff --git a/board/altera/socfpga_cyclone5/pinmux_config.c b/board/altera/socfpga_cyclone5/pinmux_config.c
 546 index 730067e..cfd74cd 100644
 547 --- a/board/altera/socfpga_cyclone5/pinmux_config.c
 548 +++ b/board/altera/socfpga_cyclone5/pinmux_config.c
 549 @@ -23,7 +23,7 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
 550         0, /* EMACIO18 */
 551         0, /* EMACIO19 */
 552         3, /* FLASHIO0 */
 553 -       3, /* FLASHIO1 */
 554 +       0, /* FLASHIO1 */
 555         3, /* FLASHIO2 */
 556         3, /* FLASHIO3 */
 557         0, /* FLASHIO4 */
 558 @@ -34,25 +34,25 @@ unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
 559         3, /* FLASHIO9 */
 560         3, /* FLASHIO10 */
 561         3, /* FLASHIO11 */
 562 -       3, /* GENERALIO0 */
 563 -       3, /* GENERALIO1 */
 564 -       3, /* GENERALIO2 */
 565 -       3, /* GENERALIO3 */
 566 -       3, /* GENERALIO4 */
 567 -       3, /* GENERALIO5 */
 568 -       3, /* GENERALIO6 */
 569 -       3, /* GENERALIO7 */
 570 -       3, /* GENERALIO8 */
 571 +       0, /* GENERALIO0 */
 572 +       1, /* GENERALIO1 */
 573 +       1, /* GENERALIO2 */
 574 +       1, /* GENERALIO3 */
 575 +       1, /* GENERALIO4 */
 576 +       0, /* GENERALIO5 */
 577 +       0, /* GENERALIO6 */
 578 +       0, /* GENERALIO7 */
 579 +       0, /* GENERALIO8 */
 580         3, /* GENERALIO9 */
 581         3, /* GENERALIO10 */
 582         3, /* GENERALIO11 */
 583         3, /* GENERALIO12 */
 584 -       2, /* GENERALIO13 */
 585 -       2, /* GENERALIO14 */
 586 -       3, /* GENERALIO15 */
 587 -       3, /* GENERALIO16 */
 588 -       2, /* GENERALIO17 */
 589 -       2, /* GENERALIO18 */
 590 +       0, /* GENERALIO13 */
 591 +       0, /* GENERALIO14 */
 592 +       1, /* GENERALIO15 */
 593 +       1, /* GENERALIO16 */
 594 +       1, /* GENERALIO17 */
 595 +       1, /* GENERALIO18 */
 596         0, /* GENERALIO19 */
 597         0, /* GENERALIO20 */
 598         0, /* GENERALIO21 */
 599 diff --git a/board/altera/socfpga_cyclone5/pinmux_config.h b/board/altera/socfpga_cyclone5/pinmux_config.h
 600 index fb483ab..64c750a 100644
 601 --- a/board/altera/socfpga_cyclone5/pinmux_config.h
 602 +++ b/board/altera/socfpga_cyclone5/pinmux_config.h
 603 @@ -11,15 +11,15 @@
 604  #define CONFIG_HPS_UART0 (1)
 605  #define CONFIG_HPS_UART1 (0)
 606  #define CONFIG_HPS_TRACE (0)
 607 -#define CONFIG_HPS_I2C0 (1)
 608 -#define CONFIG_HPS_I2C1 (0)
 609 +#define CONFIG_HPS_I2C0 (0)
 610 +#define CONFIG_HPS_I2C1 (1)
 611  #define CONFIG_HPS_I2C2 (0)
 612  #define CONFIG_HPS_I2C3 (0)
 613  #define CONFIG_HPS_SPIM0 (1)
 614 -#define CONFIG_HPS_SPIM1 (0)
 615 +#define CONFIG_HPS_SPIM1 (1)
 616  #define CONFIG_HPS_SPIS0 (0)
 617  #define CONFIG_HPS_SPIS1 (0)
 618 -#define CONFIG_HPS_CAN0 (1)
 619 +#define CONFIG_HPS_CAN0 (0)
 620  #define CONFIG_HPS_CAN1 (0)
 621
 622  #define CONFIG_HPS_SDMMC_BUSWIDTH (4)
 623 diff --git a/board/altera/socfpga_cyclone5/sdram/sdram_config.h b/board/altera/socfpga_cyclone5/sdram/sdram_config.h
 624 index b90d6f3..dd027ef 100755
 625 --- a/board/altera/socfpga_cyclone5/sdram/sdram_config.h
 626 +++ b/board/altera/socfpga_cyclone5/sdram/sdram_config.h
 627 @@ -4,16 +4,16 @@
 628  #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE                 (2)
 629  #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL                   (8)
 630  #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER               (0)
 631 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   (1)
 632 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               (1)
 633 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN                   (0)
 634 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN               (0)
 635  #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN               (1)
 636  #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT             (10)
 637  #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN                        (0)
 638  #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS                        (0)
 639 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        (6)
 640 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        (8)
 641  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  (0)
 642 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 (7)
 643 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        (4)
 644 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 (11)
 645 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        (3)
 646  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        (12)
 647  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        (104)
 648  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            (3120)
 649 @@ -21,7 +21,7 @@
 650  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              (6)
 651  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              (6)
 652  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             (4)
 653 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        (4)
 654 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        (3)
 655  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        (14)
 656  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 (20)
 657  #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        (4)
 658 @@ -33,7 +33,7 @@
 659  #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS               (15)
 660  #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS              (3)
 661  #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS                        (1)
 662 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             (40)
 663 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH             (32)
 664  #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH           (8)
 665  #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN                 (0)
 666  #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL                 (2)
 667 diff --git a/board/altera/socfpga_cyclone5/sdram/sequencer_auto.h b/board/altera/socfpga_cyclone5/sdram/sequencer_auto.h
 668 index e8c5484..919676d 100644
 669 --- a/board/altera/socfpga_cyclone5/sdram/sequencer_auto.h
 670 +++ b/board/altera/socfpga_cyclone5/sdram/sequencer_auto.h
 671 @@ -34,7 +34,7 @@
 672  #define __RW_MGR_ac_read_en 0x21
 673  #define __RW_MGR_ac_mrs3_mirr 0x0C
 674  #define __RW_MGR_ac_mrs2 0x05
 675 -#define __RW_MGR_CONTENT_ac_mrs1 0x10090044
 676 +#define __RW_MGR_CONTENT_ac_mrs1 0x10090006
 677  #define __RW_MGR_CONTENT_ac_mrs3 0x100B0000
 678  #define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000
 679  #define __RW_MGR_CONTENT_ac_act_1 0x106B0000
 680 @@ -46,8 +46,8 @@
 681  #define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000
 682  #define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008
 683  #define __RW_MGR_CONTENT_ac_pre_all 0x10280400
 684 -#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080431
 685 -#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080530
 686 +#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080471
 687 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080570
 688  #define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000
 689  #define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008
 690  #define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008
 691 @@ -55,21 +55,21 @@
 692  #define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008
 693  #define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000
 694  #define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000
 695 -#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024
 696 +#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0006
 697  #define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008
 698  #define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000
 699 -#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804C8
 700 +#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804E8
 701  #define __RW_MGR_CONTENT_ac_zqcl 0x10380400
 702  #define __RW_MGR_CONTENT_ac_write_predata 0x38F80000
 703 -#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080449
 704 +#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080469
 705  #define __RW_MGR_CONTENT_ac_ref 0x10480000
 706  #define __RW_MGR_CONTENT_ac_nop 0x30780000
 707  #define __RW_MGR_CONTENT_ac_rdimm 0x10780000
 708 -#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090010
 709 +#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090218
 710  #define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000
 711  #define __RW_MGR_CONTENT_ac_read_en 0x33780000
 712  #define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
 713 -#define __RW_MGR_CONTENT_ac_mrs2 0x100A0008
 714 +#define __RW_MGR_CONTENT_ac_mrs2 0x100A0218
 715
 716  #define __RW_MGR_READ_B2B_WAIT2 0x6A
 717  #define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
 718 diff --git a/board/altera/socfpga_cyclone5/sdram/sequencer_auto_ac_init.c b/board/altera/socfpga_cyclone5/sdram/sequencer_auto_ac_init.c
 719 index e16efa1..20b4ca1 100644
 720 --- a/board/altera/socfpga_cyclone5/sdram/sequencer_auto_ac_init.c
 721 +++ b/board/altera/socfpga_cyclone5/sdram/sequencer_auto_ac_init.c
 722 @@ -6,16 +6,16 @@ const alt_u32 ac_rom_init[36] =
 723  {
 724         0x20700000,
 725         0x20780000,
 726 -       0x10080431,
 727 -       0x10080530,
 728 -       0x10090044,
 729 -       0x100a0008,
 730 +       0x10080471,
 731 +       0x10080570,
 732 +       0x10090006,
 733 +       0x100a0218,
 734         0x100b0000,
 735         0x10380400,
 736 -       0x10080449,
 737 -       0x100804c8,
 738 -       0x100a0024,
 739 -       0x10090010,
 740 +       0x10080469,
 741 +       0x100804e8,
 742 +       0x100a0006,
 743 +       0x10090218,
 744         0x100b0000,
 745         0x30780000,
 746         0x38780000,
 747 diff --git a/board/altera/socfpga_cyclone5/sdram/sequencer_defines.h b/board/altera/socfpga_cyclone5/sdram/sequencer_defines.h
 748 index 52faf3f..b85b85c 100644
 749 --- a/board/altera/socfpga_cyclone5/sdram/sequencer_defines.h
 750 +++ b/board/altera/socfpga_cyclone5/sdram/sequencer_defines.h
 751 @@ -1,28 +1,28 @@
 752  #ifndef _SEQUENCER_DEFINES_H_
 753  #define _SEQUENCER_DEFINES_H_
 754
 755 -#define AC_ROM_MR1_MIRR 0000000100100
 756 +#define AC_ROM_MR1_MIRR 0000000000110
 757  #define AC_ROM_MR1_OCD_ENABLE
 758 -#define AC_ROM_MR2_MIRR 0000000010000
 759 +#define AC_ROM_MR2_MIRR 0001000011000
 760  #define AC_ROM_MR3_MIRR 0000000000000
 761  #define AC_ROM_MR0_CALIB
 762 -#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
 763 -#define AC_ROM_MR0_DLL_RESET 0010100110000
 764 -#define AC_ROM_MR0_MIRR 0010001001001
 765 -#define AC_ROM_MR0 0010000110001
 766 -#define AC_ROM_MR1 0000001000100
 767 -#define AC_ROM_MR2 0000000001000
 768 +#define AC_ROM_MR0_DLL_RESET_MIRR 0010011101000
 769 +#define AC_ROM_MR0_DLL_RESET 0010101110000
 770 +#define AC_ROM_MR0_MIRR 0010001101001
 771 +#define AC_ROM_MR0 0010001110001
 772 +#define AC_ROM_MR1 0000000000110
 773 +#define AC_ROM_MR2 0001000011000
 774  #define AC_ROM_MR3 0000000000000
 775  #define AFI_CLK_FREQ 401
 776  #define AFI_RATE_RATIO 1
 777  #define ARRIAVGZ 0
 778  #define ARRIAV 0
 779 -#define AVL_CLK_FREQ 67
 780 +#define AVL_CLK_FREQ 81
 781  #define BFM_MODE 0
 782  #define BURST2 0
 783  #define CALIBRATE_BIT_SLIPS 0
 784 -#define CALIB_LFIFO_OFFSET 7
 785 -#define CALIB_VFIFO_OFFSET 5
 786 +#define CALIB_LFIFO_OFFSET 11
 787 +#define CALIB_VFIFO_OFFSET 9
 788  #define CYCLONEV 1
 789  #define DDR2 0
 790  #define DDR3 1
 791 @@ -89,20 +89,20 @@
 792  #define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
 793  #define RW_MGR_MEM_CLK_EN_WIDTH 1
 794  #define RW_MGR_MEM_CONTROL_WIDTH 1
 795 -#define RW_MGR_MEM_DATA_MASK_WIDTH 5
 796 -#define RW_MGR_MEM_DATA_WIDTH 40
 797 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4
 798 +#define RW_MGR_MEM_DATA_WIDTH 32
 799  #define RW_MGR_MEM_DQ_PER_READ_DQS 8
 800  #define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
 801 -#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
 802 -#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
 803 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
 804 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
 805  #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
 806  #define RW_MGR_MEM_NUMBER_OF_RANKS 1
 807  #define RW_MGR_MEM_ODT_WIDTH 1
 808  #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
 809  #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
 810  #define RW_MGR_MR0_BL 1
 811 -#define RW_MGR_MR0_CAS_LATENCY 3
 812 -#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
 813 +#define RW_MGR_MR0_CAS_LATENCY 7
 814 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
 815  #define RW_MGR_WRITE_TO_DEBUG_READ 1.0
 816  #define SKEW_CALIBRATION 0
 817  #define STATIC_FULL_CALIBRATION 1
 818 --
 819 1.9.0
 820