2 config BR2_ARM_CPU_HAS_NEON
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
13 config BR2_ARM_CPU_HAS_VFPV2
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
37 config BR2_ARM_CPU_HAS_THUMB
40 config BR2_ARM_CPU_HAS_THUMB2
43 config BR2_ARM_CPU_ARMV4
46 config BR2_ARM_CPU_ARMV5
49 config BR2_ARM_CPU_ARMV6
52 config BR2_ARM_CPU_ARMV7A
56 prompt "Target Architecture Variant"
57 depends on BR2_arm || BR2_armeb
60 Specific CPU variant to use
64 select BR2_ARM_CPU_HAS_ARM
65 select BR2_ARM_CPU_HAS_THUMB
66 select BR2_ARM_CPU_ARMV4
69 select BR2_ARM_CPU_HAS_ARM
70 select BR2_ARM_CPU_HAS_THUMB
71 select BR2_ARM_CPU_ARMV4
74 select BR2_ARM_CPU_HAS_ARM
75 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
76 select BR2_ARM_CPU_HAS_THUMB
77 select BR2_ARM_CPU_ARMV5
78 config BR2_arm1136jf_s
80 select BR2_ARM_CPU_HAS_ARM
81 select BR2_ARM_CPU_HAS_VFPV2
82 select BR2_ARM_CPU_HAS_THUMB
83 select BR2_ARM_CPU_ARMV6
84 config BR2_arm1176jz_s
86 select BR2_ARM_CPU_HAS_ARM
87 select BR2_ARM_CPU_HAS_THUMB
88 select BR2_ARM_CPU_ARMV6
89 config BR2_arm1176jzf_s
91 select BR2_ARM_CPU_HAS_ARM
92 select BR2_ARM_CPU_HAS_VFPV2
93 select BR2_ARM_CPU_HAS_THUMB
94 select BR2_ARM_CPU_ARMV6
97 select BR2_ARM_CPU_HAS_ARM
98 select BR2_ARM_CPU_MAYBE_HAS_NEON
99 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
100 select BR2_ARM_CPU_HAS_THUMB2
101 select BR2_ARM_CPU_ARMV7A
104 select BR2_ARM_CPU_HAS_ARM
105 select BR2_ARM_CPU_HAS_NEON
106 select BR2_ARM_CPU_HAS_VFPV4
107 select BR2_ARM_CPU_HAS_THUMB2
108 select BR2_ARM_CPU_ARMV7A
111 select BR2_ARM_CPU_HAS_ARM
112 select BR2_ARM_CPU_HAS_NEON
113 select BR2_ARM_CPU_HAS_VFPV3
114 select BR2_ARM_CPU_HAS_THUMB2
115 select BR2_ARM_CPU_ARMV7A
118 select BR2_ARM_CPU_HAS_ARM
119 select BR2_ARM_CPU_MAYBE_HAS_NEON
120 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
121 select BR2_ARM_CPU_HAS_THUMB2
122 select BR2_ARM_CPU_ARMV7A
123 config BR2_cortex_a12
125 select BR2_ARM_CPU_HAS_ARM
126 select BR2_ARM_CPU_HAS_NEON
127 select BR2_ARM_CPU_HAS_VFPV4
128 select BR2_ARM_CPU_HAS_THUMB2
129 select BR2_ARM_CPU_ARMV7A
130 config BR2_cortex_a15
132 select BR2_ARM_CPU_HAS_ARM
133 select BR2_ARM_CPU_HAS_NEON
134 select BR2_ARM_CPU_HAS_VFPV4
135 select BR2_ARM_CPU_HAS_THUMB2
136 select BR2_ARM_CPU_ARMV7A
139 select BR2_ARM_CPU_HAS_ARM
140 select BR2_ARM_CPU_ARMV4
143 select BR2_ARM_CPU_HAS_ARM
144 select BR2_ARM_CPU_HAS_VFPV3
145 select BR2_ARM_CPU_ARMV7A
147 bool "strongarm sa110/sa1100"
148 select BR2_ARM_CPU_HAS_ARM
149 select BR2_ARM_CPU_ARMV4
152 select BR2_ARM_CPU_HAS_ARM
153 select BR2_ARM_CPU_HAS_THUMB
154 select BR2_ARM_CPU_ARMV5
157 select BR2_ARM_CPU_HAS_ARM
158 select BR2_ARM_CPU_ARMV5
163 depends on BR2_arm || BR2_armeb
166 Application Binary Interface to use. The Application Binary
167 Interface describes the calling conventions (how arguments
168 are passed to functions, how the return value is passed, how
169 system calls are made, etc.).
174 The EABI is currently the standard ARM ABI, which is used in
175 most projects. It supports both the 'soft' floating point
176 model (in which floating point instructions are emulated in
177 software) and the 'softfp' floating point model (in which
178 floating point instructions are executed using an hardware
179 floating point unit, but floating point arguments to
180 functions are passed in integer registers).
182 The 'softfp' floating point model is link-compatible with
183 the 'soft' floating point model, i.e you can link a library
184 built 'soft' with some other code built 'softfp'.
186 However, passing the floating point arguments in integer
187 registers is a bit inefficient, so if your ARM processor has
188 a floating point unit, and you don't have pre-compiled
189 'soft' or 'softfp' code, using the EABIhf ABI will provide
190 better floating point performances.
192 If your processor does not have a floating point unit, then
193 you must use this ABI.
195 config BR2_ARM_EABIHF
197 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2 || BR2_ARM_CPU_HAS_VFPV2
199 The EABIhf is an extension of EABI which supports the 'hard'
200 floating point model. This model uses the floating point
201 unit to execute floating point instructions, and passes
202 floating point arguments in floating point registers.
204 It is more efficient than EABI for floating point related
205 workload. However, it does not allow to link against code
206 that has been pre-built for the 'soft' or 'softfp' floating
209 If your processor has a floating point unit, and you don't
210 depend on existing pre-compiled code, this option is most
211 likely the best choice.
215 config BR2_ARM_ENABLE_NEON
216 bool "Enable NEON SIMD extension support"
217 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
218 select BR2_ARM_CPU_HAS_NEON
220 For some CPU cores, the NEON SIMD extension is optional.
221 Select this option if you are certain your particular
222 implementation has NEON support and you want to use it.
225 prompt "Floating point strategy"
226 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
227 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
228 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
229 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
230 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
232 config BR2_ARM_SOFT_FLOAT
234 depends on BR2_ARM_EABI
235 select BR2_SOFT_FLOAT
237 This option allows to use software emulated floating
238 point. It should be used for ARM cores that do not include a
239 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
240 example) or certain ARMv6 cores.
242 config BR2_ARM_FPU_VFPV2
244 depends on BR2_ARM_CPU_HAS_VFPV2 || BR2_ARM_CPU_MAYBE_HAS_VFPV2
246 This option allows to use the VFPv2 floating point unit, as
247 available in some ARMv5 processors (ARM926EJ-S) and some
248 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
251 Note that this option is also safe to use for newer cores
252 such as Cortex-A, because the VFPv3 and VFPv4 units are
253 backward compatible with VFPv2.
255 config BR2_ARM_FPU_VFPV3
257 depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
259 This option allows to use the VFPv3 floating point unit, as
260 available in some ARMv7 processors (Cortex-A{8, 9}). This
261 option requires a VFPv3 unit that has 32 double-precision
262 registers, which is not necessarily the case in all SOCs
263 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
264 instead, which is guaranteed to work on all Cortex-A{8, 9}.
266 Note that this option is also safe to use for newer cores
267 that have a VFPv4 unit, because VFPv4 is backward compatible
268 with VFPv3. They must of course also have 32
269 double-precision registers.
271 config BR2_ARM_FPU_VFPV3D16
273 depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
275 This option allows to use the VFPv3 floating point unit, as
276 available in some ARMv7 processors (Cortex-A{8, 9}). This
277 option requires a VFPv3 unit that has 16 double-precision
278 registers, which is generally the case in all SOCs based on
279 Cortex-A{8, 9}, even though VFPv3 is technically optional on
280 Cortex-A9. This is the safest option for those cores.
282 Note that this option is also safe to use for newer cores
283 such that have a VFPv4 unit, because the VFPv4 is backward
284 compatible with VFPv3.
286 config BR2_ARM_FPU_VFPV4
288 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
290 This option allows to use the VFPv4 floating point unit, as
291 available in some ARMv7 processors (Cortex-A{5, 7, 12,
292 15}). This option requires a VFPv4 unit that has 32
293 double-precision registers, which is not necessarily the
294 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
295 unsure, you should probably use VFPv4-D16 instead.
297 Note that if you want binary code that works on all ARMv7
298 cores, including the earlier Cortex-A{8, 9}, you should
299 instead select VFPv3.
301 config BR2_ARM_FPU_VFPV4D16
303 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
305 This option allows to use the VFPv4 floating point unit, as
306 available in some ARMv7 processors (Cortex-A{5, 7, 12,
307 15}). This option requires a VFPv4 unit that has 16
308 double-precision registers, which is always available on
309 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
312 Note that if you want binary code that works on all ARMv7
313 cores, including the earlier Cortex-A{8, 9}, you should
314 instead select VFPv3-D16.
316 config BR2_ARM_FPU_NEON
318 depends on BR2_ARM_CPU_HAS_NEON
320 This option allows to use the NEON SIMD unit, as available
321 in some ARMv7 processors, as a floating-point unit. It
322 should however be noted that using NEON for floating point
323 operations doesn't provide a complete compatibility with the
326 config BR2_ARM_FPU_NEON_VFPV4
328 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
329 depends on BR2_ARM_CPU_HAS_NEON
331 This option allows to use both the VFPv4 and the NEON SIMD
332 units for floating point operations. Note that some ARMv7
333 cores do not necessarily have VFPv4 and/or NEON support, for
334 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
340 prompt "ARM instruction set"
342 config BR2_ARM_INSTRUCTIONS_ARM
344 depends on BR2_ARM_CPU_HAS_ARM
346 This option instructs the compiler to generate regular ARM
347 instructions, that are all 32 bits wide.
349 config BR2_ARM_INSTRUCTIONS_THUMB
351 depends on BR2_ARM_CPU_HAS_THUMB
353 This option instructions the compiler to generate Thumb
354 instructions, which allows to mix 16 bits instructions and
355 32 bits instructions. This generally provides a much smaller
356 compiled binary size.
358 config BR2_ARM_INSTRUCTIONS_THUMB2
360 depends on BR2_ARM_CPU_HAS_THUMB2
362 This option instructions the compiler to generate Thumb2
363 instructions, which allows to mix 16 bits instructions and
364 32 bits instructions. This generally provides a much smaller
365 compiled binary size.
370 default "arm" if BR2_arm
371 default "armeb" if BR2_armeb
374 default "LITTLE" if BR2_arm
375 default "BIG" if BR2_armeb
377 config BR2_ARCH_HAS_ATOMICS
380 config BR2_GCC_TARGET_CPU
381 default "arm920t" if BR2_arm920t
382 default "arm922t" if BR2_arm922t
383 default "arm926ej-s" if BR2_arm926t
384 default "arm1136j-s" if BR2_arm1136j_s
385 default "arm1136jf-s" if BR2_arm1136jf_s
386 default "arm1176jz-s" if BR2_arm1176jz_s
387 default "arm1176jzf-s" if BR2_arm1176jzf_s
388 default "cortex-a5" if BR2_cortex_a5
389 default "cortex-a7" if BR2_cortex_a7
390 default "cortex-a8" if BR2_cortex_a8
391 default "cortex-a9" if BR2_cortex_a9
392 default "cortex-a12" if BR2_cortex_a12
393 default "cortex-a15" if BR2_cortex_a15
394 default "fa526" if BR2_fa526
395 default "marvell-pj4" if BR2_pj4
396 default "strongarm" if BR2_strongarm
397 default "xscale" if BR2_xscale
398 default "iwmmxt" if BR2_iwmmxt
400 config BR2_GCC_TARGET_ABI
401 default "aapcs-linux"
403 config BR2_GCC_TARGET_FPU
404 default "vfp" if BR2_ARM_FPU_VFPV2
405 default "vfpv3" if BR2_ARM_FPU_VFPV3
406 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
407 default "vfpv4" if BR2_ARM_FPU_VFPV4
408 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
409 default "neon" if BR2_ARM_FPU_NEON
410 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
412 config BR2_GCC_TARGET_FLOAT_ABI
413 default "soft" if BR2_ARM_SOFT_FLOAT
414 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
415 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
417 config BR2_GCC_TARGET_MODE
418 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
419 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2