1 From a3e08beea8bf5e96e1237eef4a82f4a2fdd5286b Mon Sep 17 00:00:00 2001
2 From: Gregory Hermant <gregory.hermant@calao-systems.com>
3 Date: Thu, 19 Jul 2012 14:19:59 +0200
4 Subject: [PATCH] Add support for the Calao-systems QIL-A9260
7 Signed-off-by: Gregory Hermant <gregory.hermant@calao-systems.com>
9 board/qil_a9260/nandflash/Makefile | 122 ++++++++++++++
10 board/qil_a9260/nandflash/qil-a9260.h | 109 ++++++++++++
11 board/qil_a9260/qil_a9260.c | 298 +++++++++++++++++++++++++++++++++
14 5 files changed, 541 insertions(+), 1 deletions(-)
15 create mode 100644 board/qil_a9260/nandflash/Makefile
16 create mode 100644 board/qil_a9260/nandflash/qil-a9260.h
17 create mode 100644 board/qil_a9260/qil_a9260.c
19 diff --git a/board/qil_a9260/nandflash/Makefile b/board/qil_a9260/nandflash/Makefile
21 index 0000000..209a25f
23 +++ b/board/qil_a9260/nandflash/Makefile
25 +# TODO: set this appropriately for your local toolchain
30 +CROSS_COMPILE=arm-elf-
35 +BOOTSTRAP_PATH=../../..
37 +# NandFlashBoot Configuration for QIL-A9260
39 +# Target name (case sensitive!!!)
41 +# Board name (case sensitive!!!)
43 +# Link Address and Top_of_Memory
45 +TOP_OF_MEMORY=0x301000
46 +# Name of current directory
50 +BOOT_NAME=$(PROJECT)_$(BOARD)
53 +INCL=./$(BOOTSTRAP_PATH)/board/$(BOARD)/$(PROJECT)
55 +ifeq ($(TOOLCHAIN), gcc)
57 +AS=$(CROSS_COMPILE)gcc
58 +CC=$(CROSS_COMPILE)gcc
59 +LD=$(CROSS_COMPILE)gcc
60 +NM= $(CROSS_COMPILE)nm
61 +SIZE=$(CROSS_COMPILE)size
62 +OBJCOPY=$(CROSS_COMPILE)objcopy
63 +OBJDUMP=$(CROSS_COMPILE)objdump
64 +CCFLAGS=-g -mcpu=arm926ej-s -Os -Wall -D$(TARGET) -D$(BOARD) -I$(INCL)
65 +ASFLAGS=-g -mcpu=arm926ej-s -c -Os -Wall -D$(TARGET) -D$(BOARD) -I$(INCL) -DTOP_OF_MEM=$(TOP_OF_MEMORY)
68 +# -Wl,...: tell GCC to pass this to linker.
69 +# -Map: create map file
70 +# --cref: add cross reference to map file
71 +LDFLAGS+=-nostartfiles -nostdlib -Wl,-Map=$(BOOT_NAME).map,--cref
72 +LDFLAGS+=-T $(BOOTSTRAP_PATH)/elf32-littlearm.lds -Ttext $(LINK_ADDR)
96 +ifeq ($(TOOLCHAIN), gcc)
97 +$(BOOT_NAME): $(OBJS)
98 + $(LD) $(LDFLAGS) -n -o $(BOOT_NAME).elf $(OBJS)
99 + $(OBJCOPY) --strip-debug --strip-unneeded $(BOOT_NAME).elf -O binary $(BOOT_NAME).bin
103 +$(BOARD).o: $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c
104 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/board/$(BOARD)/$(BOARD).c -o $(BOARD).o
106 +main.o: $(BOOTSTRAP_PATH)/main.c
107 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/main.c -o main.o
109 +gpio.o: $(BOOTSTRAP_PATH)/driver/gpio.c
110 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/gpio.c -o gpio.o
112 +pmc.o: $(BOOTSTRAP_PATH)/driver/pmc.c
113 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/pmc.c -o pmc.o
115 +debug.o: $(BOOTSTRAP_PATH)/driver/debug.c
116 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/debug.c -o debug.o
118 +sdramc.o: $(BOOTSTRAP_PATH)/driver/sdramc.c
119 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/sdramc.c -o sdramc.o
121 +dataflash.o: $(BOOTSTRAP_PATH)/driver/dataflash.c
122 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/dataflash.c -o dataflash.o
124 +nandflash.o: $(BOOTSTRAP_PATH)/driver/nandflash.c
125 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/driver/nandflash.c -o nandflash.o
127 +crt0_gnu.o: $(BOOTSTRAP_PATH)/crt0_gnu.S
128 + $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/crt0_gnu.S -o crt0_gnu.o
130 +div0.o: $(BOOTSTRAP_PATH)/lib/div0.c
131 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/div0.c -o div0.o
133 +string.o: $(BOOTSTRAP_PATH)/lib/string.c
134 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/string.c -o string.o
136 +udiv.o: $(BOOTSTRAP_PATH)/lib/udiv.c
137 + $(CC) -c $(CCFLAGS) $(BOOTSTRAP_PATH)/lib/udiv.c -o udiv.o
139 +_udivsi3.o: $(BOOTSTRAP_PATH)/lib/_udivsi3.S
140 + $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_udivsi3.S -o _udivsi3.o
142 +_umodsi3.o: $(BOOTSTRAP_PATH)/lib/_umodsi3.S
143 + $(AS) $(ASFLAGS) $(BOOTSTRAP_PATH)/lib/_umodsi3.S -o _umodsi3.o
146 + $(ERASE_FCT) *.o *.bin *.elf *.map
147 diff --git a/board/qil_a9260/nandflash/qil-a9260.h b/board/qil_a9260/nandflash/qil-a9260.h
149 index 0000000..c87002e
151 +++ b/board/qil_a9260/nandflash/qil-a9260.h
153 +/* ----------------------------------------------------------------------------
154 + * ATMEL Microcontroller Software Support - ROUSSET -
155 + * ----------------------------------------------------------------------------
156 + * Copyright (c) 2006, Atmel Corporation
158 + * All rights reserved.
160 + * Redistribution and use in source and binary forms, with or without
161 + * modification, are permitted provided that the following conditions are met:
163 + * - Redistributions of source code must retain the above copyright notice,
164 + * this list of conditions and the disclaimer below.
166 + * Atmel's name may not be used to endorse or promote products derived from
167 + * this software without specific prior written permission.
169 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
170 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
171 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
172 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
173 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
174 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
175 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
176 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
177 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
178 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
179 + * ----------------------------------------------------------------------------
180 + * File Name : qil-a9260.h
182 + * Creation : GH July 19th 2012
183 + *-----------------------------------------------------------------------------
185 +#ifndef _QIL_A9260_H
186 +#define _QIL_A9260_H
188 +/* ******************************************************************* */
191 +/* The main oscillator is enabled as soon as possible in the c_startup */
192 +/* and MCK is switched on the main oscillator. */
193 +/* PLL initialization is done later in the hw_init() function */
194 +/* ******************************************************************* */
195 +#define MASTER_CLOCK (180000000/2)
196 +#define PLL_LOCK_TIMEOUT 1000000
198 +#define PLLA_SETTINGS 0x20593F06
199 +#define PLLB_SETTINGS 0x10483F0E
201 +/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
202 +#define MCKR_SETTINGS (AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2)
203 +#define MCKR_CSS_SETTINGS (AT91C_PMC_CSS_PLLA_CLK | MCKR_SETTINGS)
205 +/* ******************************************************************* */
206 +/* NandFlash Settings */
208 +/* ******************************************************************* */
209 +#define AT91C_SMARTMEDIA_BASE 0x40000000
211 +#define AT91_SMART_MEDIA_ALE (1 << 21) /* our ALE is AD21 */
212 +#define AT91_SMART_MEDIA_CLE (1 << 22) /* our CLE is AD22 */
214 +#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
215 +#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
217 +#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
220 +/* ******************************************************************** */
221 +/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 90000000.*/
222 +/* Please refer to SMC section in AT91SAM datasheet to learn how */
223 +/* to generate these values. */
224 +/* ******************************************************************** */
225 +#define AT91C_SM_NWE_SETUP (1 << 0)
226 +#define AT91C_SM_NCS_WR_SETUP (0 << 8)
227 +#define AT91C_SM_NRD_SETUP (1 << 16)
228 +#define AT91C_SM_NCS_RD_SETUP (0 << 24)
230 +#define AT91C_SM_NWE_PULSE (3 << 0)
231 +#define AT91C_SM_NCS_WR_PULSE (3 << 8)
232 +#define AT91C_SM_NRD_PULSE (3 << 16)
233 +#define AT91C_SM_NCS_RD_PULSE (3 << 24)
235 +#define AT91C_SM_NWE_CYCLE (5 << 0)
236 +#define AT91C_SM_NRD_CYCLE (5 << 16)
237 +#define AT91C_SM_TDF (2 << 16)
239 +/* ******************************************************************* */
240 +/* BootStrap Settings */
242 +/* ******************************************************************* */
243 +#define IMG_ADDRESS 0x20000 /* Image Address in NandFlash */
244 +#define IMG_SIZE 0x40000 /* Image Size in NandFlash */
246 +#define MACH_TYPE 0x6AF /* QIL-A9260 */
247 +#define JUMP_ADDR 0x23F00000 /* Final Jump Address */
249 +/* ******************************************************************* */
250 +/* Application Settings */
251 +/* ******************************************************************* */
253 +#undef CFG_DATAFLASH
255 +#define CFG_NANDFLASH
256 +#undef NANDFLASH_SMALL_BLOCKS /* NANDFLASH_LARGE_BLOCKS used instead */
261 +#endif /* _QIL_A9260_H */
262 diff --git a/board/qil_a9260/qil_a9260.c b/board/qil_a9260/qil_a9260.c
264 index 0000000..ae122e7
266 +++ b/board/qil_a9260/qil_a9260.c
268 +/* ----------------------------------------------------------------------------
269 + * ATMEL Microcontroller Software Support - ROUSSET -
270 + * ----------------------------------------------------------------------------
271 + * Copyright (c) 2006, Atmel Corporation
273 + * All rights reserved.
275 + * Redistribution and use in source and binary forms, with or without
276 + * modification, are permitted provided that the following conditions are met:
278 + * - Redistributions of source code must retain the above copyright notice,
279 + * this list of conditions and the disclaiimer below.
281 + * Atmel's name may not be used to endorse or promote products derived from
282 + * this software without specific prior written permission.
284 + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
285 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
286 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
287 + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
288 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
289 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
290 + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
291 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
292 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
293 + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
294 + * ----------------------------------------------------------------------------
295 + * File Name : qil_a9260.c
297 + * Creation : GH July 19th 2012
298 + *-----------------------------------------------------------------------------
300 +#include "../../include/part.h"
301 +#include "../../include/gpio.h"
302 +#include "../../include/pmc.h"
303 +#include "../../include/debug.h"
304 +#include "../../include/sdramc.h"
305 +#include "../../include/main.h"
306 +#ifdef CFG_NANDFLASH
307 +#include "../../include/nandflash.h"
309 +#ifdef CFG_DATAFLASH
310 +#include "../../include/dataflash.h"
313 +static inline unsigned int get_cp15(void)
315 + unsigned int value;
316 + __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value));
320 +static inline void set_cp15(unsigned int value)
322 + __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value));
326 +/*----------------------------------------------------------------------------*/
328 +/* \brief This function performs very low level HW initialization */
329 +/* This function is invoked as soon as possible during the c_startup */
330 +/* The bss segment must be initialized */
331 +/*----------------------------------------------------------------------------*/
336 + /* Configure PIOs */
337 + const struct pio_desc hw_pio[] = {
339 + {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
340 + {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
342 + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
345 + /* Disable watchdog */
346 + writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
348 + /* At this stage the main oscillator is supposed to be enabled
349 + * PCK = MCK = MOSC */
351 + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
352 + pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
354 + /* PCK = PLLA = 2 * MCK */
355 + pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
356 + /* Switch MCK on PLLA output */
357 + pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
359 + /* Configure PLLB */
360 + pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
362 + /* Configure CP15 */
367 + /* Configure the PIO controller */
370 + /* Configure the EBI Slave Slot Cycle to 64 */
371 + writel( (readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3));
374 + /* Enable Debug messages on the DBGU */
375 + dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
377 + dbg_print("Start AT91Bootstrap...\n\r");
378 +#endif /* CFG_DEBUG */
381 + /* Initialize the matrix */
382 + writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA);
384 + /* Configure SDRAM Controller */
385 + sdram_init( AT91C_SDRAMC_NC_9 |
386 + AT91C_SDRAMC_NR_13 |
387 + AT91C_SDRAMC_CAS_2 |
388 + AT91C_SDRAMC_NB_4_BANKS |
389 + AT91C_SDRAMC_DBW_32_BITS |
390 + AT91C_SDRAMC_TWR_2 |
391 + AT91C_SDRAMC_TRC_7 |
392 + AT91C_SDRAMC_TRP_2 |
393 + AT91C_SDRAMC_TRCD_2 |
394 + AT91C_SDRAMC_TRAS_5 |
395 + AT91C_SDRAMC_TXSR_8, /* Control Register */
396 + (MASTER_CLOCK * 7)/1000000, /* Refresh Timer Register */
397 + AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */
400 +#endif /* CFG_SDRAM */
402 +#endif /* CFG_HW_INIT */
405 +/*------------------------------------------------------------------------------*/
406 +/* \fn sdramc_hw_init */
407 +/* \brief This function performs SDRAMC HW initialization */
408 +/*------------------------------------------------------------------------------*/
409 +void sdramc_hw_init(void)
411 + /* Configure PIOs */
412 +/* const struct pio_desc sdramc_pio[] = {
413 + {"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
414 + {"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
415 + {"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
416 + {"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
417 + {"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
418 + {"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
419 + {"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
420 + {"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
421 + {"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
422 + {"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
423 + {"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
424 + {"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
425 + {"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
426 + {"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
427 + {"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
428 + {"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
429 + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
432 + /* Configure the SDRAMC PIO controller to output PCK0 */
433 +/* pio_setup(sdramc_pio); */
435 + writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
436 + writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
439 +#endif /* CFG_SDRAM */
441 +#ifdef CFG_DATAFLASH
443 +/*------------------------------------------------------------------------------*/
444 +/* \fn df_recovery */
445 +/* \brief This function erases DataFlash Page 0 if USR PB is pressed */
446 +/* during boot sequence */
447 +/*------------------------------------------------------------------------------*/
448 +void df_recovery(AT91PS_DF pDf)
450 +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
451 + /* Configure PIOs */
452 + const struct pio_desc usrpb_pio[] = {
453 + {"USRPB", AT91C_PIN_PB(10), 0, PIO_PULLUP, PIO_INPUT},
454 + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
457 + /* Configure the PIO controller */
458 + writel((1 << AT91C_ID_PIOB), PMC_PCER + AT91C_BASE_PMC);
459 + pio_setup(usrpb_pio);
461 + /* If USR PB is pressed during Boot sequence */
462 + /* Erase DataFlash Page 0*/
463 + if ( !pio_get_value(AT91C_PIN_PB(10)) )
464 + df_page_erase(pDf, 0);
468 +/*------------------------------------------------------------------------------*/
469 +/* \fn df_hw_init */
470 +/* \brief This function performs DataFlash HW initialization */
471 +/*------------------------------------------------------------------------------*/
472 +void df_hw_init(void)
474 + /* Configure PIOs */
475 + const struct pio_desc df_pio[] = {
476 + {"MISO", AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
477 + {"MOSI", AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
478 + {"SPCK", AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
479 +#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
480 + {"NPCS0", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
482 + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
485 + /* Configure the PIO controller */
488 +#endif /* CFG_DATAFLASH */
492 +#ifdef CFG_NANDFLASH
493 +/*------------------------------------------------------------------------------*/
494 +/* \fn nand_recovery */
495 +/* \brief This function erases NandFlash Block 0 if USR PB is pressed */
496 +/* during boot sequence */
497 +/*------------------------------------------------------------------------------*/
498 +static void nand_recovery(void)
500 + /* Configure PIOs */
501 + const struct pio_desc usrpb_pio[] = {
502 + {"USRPB", AT91C_PIN_PB(10), 0, PIO_PULLUP, PIO_INPUT},
503 + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
506 + /* Configure the PIO controller */
507 + writel((1 << AT91C_ID_PIOB), PMC_PCER + AT91C_BASE_PMC);
508 + pio_setup(usrpb_pio);
510 + /* If USR PB is pressed during Boot sequence */
511 + /* Erase NandFlash block 0*/
512 + if (!pio_get_value(AT91C_PIN_PB(10)) )
513 + AT91F_NandEraseBlock0();
516 +/*------------------------------------------------------------------------------*/
517 +/* \fn nandflash_hw_init */
518 +/* \brief NandFlash HW init */
519 +/*------------------------------------------------------------------------------*/
520 +void nandflash_hw_init(void)
522 + /* Configure PIOs */
523 + const struct pio_desc nand_pio[] = {
524 + {"RDY_BSY", AT91C_PIN_PC(13), 0, PIO_PULLUP, PIO_INPUT},
525 + {"NANDCS", AT91C_PIN_PC(14), 0, PIO_PULLUP, PIO_OUTPUT},
526 + {(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
529 + /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
530 + writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA);
532 + /* Configure SMC CS3 */
533 + writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
534 + writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
535 + writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE) , AT91C_BASE_SMC + SMC_CYCLE3);
536 + writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE |
537 + AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | AT91C_SM_TDF) , AT91C_BASE_SMC + SMC_CTRL3);
539 + /* Configure the PIO controller */
540 + writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
541 + pio_setup(nand_pio);
546 +/*------------------------------------------------------------------------------*/
547 +/* \fn nandflash_cfg_16bits_dbw_init */
548 +/* \brief Configure SMC in 16 bits mode */
549 +/*------------------------------------------------------------------------------*/
550 +void nandflash_cfg_16bits_dbw_init(void)
552 + writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC + SMC_CTRL3);
555 +/*------------------------------------------------------------------------------*/
556 +/* \fn nandflash_cfg_8bits_dbw_init */
557 +/* \brief Configure SMC in 8 bits mode */
558 +/*------------------------------------------------------------------------------*/
559 +void nandflash_cfg_8bits_dbw_init(void)
561 + writel((readl(AT91C_BASE_SMC + SMC_CTRL3) & ~(AT91C_SMC_DBW)) | AT91C_SMC_DBW_WIDTH_EIGTH_BITS, AT91C_BASE_SMC + SMC_CTRL3);
565 +#endif /* #ifdef CFG_NANDFLASH */
566 diff --git a/crt0_gnu.S b/crt0_gnu.S
567 index 042b617..002feef 100644
570 @@ -106,6 +106,13 @@ _relocate_to_sram:
571 #endif /* CFG_NORFLASH */
574 +/* Test if main osc is bypassed */
575 + ldr r0,=AT91C_PMC_MOR
577 + ldr r2,=AT91C_CKGR_OSCBYPASS
579 + bne _init_data /* branch if OSCBYPASS=1 */
581 /* Test if main oscillator is enabled */
584 diff --git a/include/part.h b/include/part.h
585 index ba5985a..bbd33fe 100644
591 #include "AT91SAM9260_inc.h"
592 -#include "at91sam9260ek.h"
593 + #ifdef at91sam9260ek
594 + #include "at91sam9260ek.h"
596 + #include "qil-a9260.h"