6 config BR2_KERNEL_64_USERLAND_32
13 prompt "Target Architecture"
16 Select the target architecture family to build for.
19 bool "ARC (little endian)"
21 Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
22 that can be used from deeply embedded to high performance host
23 applications. Little endian.
26 bool "ARC (big endian)"
28 Synopsys' DesignWare ARC Processor Cores are a family of 32-bit CPUs
29 that can be used from deeply embedded to high performance host
30 applications. Big endian.
33 bool "ARM (little endian)"
35 ARM is a 32-bit reduced instruction set computer (RISC) instruction
36 set architecture (ISA) developed by ARM Holdings. Little endian.
38 http://en.wikipedia.org/wiki/ARM
41 bool "ARM (big endian)"
43 ARM is a 32-bit reduced instruction set computer (RISC) instruction
44 set architecture (ISA) developed by ARM Holdings. Big endian.
46 http://en.wikipedia.org/wiki/ARM
52 Aarch64 is a 64-bit architecture developed by ARM Holdings.
53 http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
54 http://en.wikipedia.org/wiki/ARM
59 The Blackfin is a family of 16 or 32-bit microprocessors developed,
60 manufactured and marketed by Analog Devices.
61 http://www.analog.com/
62 http://en.wikipedia.org/wiki/Blackfin
67 Intel i386 architecture compatible microprocessor
68 http://en.wikipedia.org/wiki/I386
72 depends on BROKEN # ice in uclibc / inet_ntoa_r
74 Motorola 68000 family microprocessor
75 http://en.wikipedia.org/wiki/M68k
77 config BR2_microblazeel
78 bool "Microblaze AXI (little endian)"
80 Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus
81 based architecture (little endian)
83 http://en.wikipedia.org/wiki/Microblaze
85 config BR2_microblazebe
86 bool "Microblaze non-AXI (big endian)"
88 Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus
89 based architecture (non-AXI, big endian)
91 http://en.wikipedia.org/wiki/Microblaze
94 bool "MIPS (big endian)"
96 MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
98 http://en.wikipedia.org/wiki/MIPS_Technologies
101 bool "MIPS (little endian)"
103 MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
105 http://en.wikipedia.org/wiki/MIPS_Technologies
108 bool "MIPS64 (big endian)"
109 select BR2_ARCH_IS_64
111 MIPS is a RISC microprocessor from MIPS Technologies. Big endian.
113 http://en.wikipedia.org/wiki/MIPS_Technologies
116 bool "MIPS64 (little endian)"
117 select BR2_ARCH_IS_64
119 MIPS is a RISC microprocessor from MIPS Technologies. Little endian.
121 http://en.wikipedia.org/wiki/MIPS_Technologies
126 Nios II is a soft core processor from Altera Corporation.
127 http://www.altera.com/
128 http://en.wikipedia.org/wiki/Nios_II
133 PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
135 http://www.power.org/
136 http://en.wikipedia.org/wiki/Powerpc
139 bool "PowerPC64 (big endian)"
140 select BR2_ARCH_IS_64
142 PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
144 http://www.power.org/
145 http://en.wikipedia.org/wiki/Powerpc
147 config BR2_powerpc64le
148 bool "PowerPC64 (little endian)"
149 select BR2_ARCH_IS_64
151 PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance.
153 http://www.power.org/
154 http://en.wikipedia.org/wiki/Powerpc
159 SuperH (or SH) is a 32-bit reduced instruction set computer (RISC)
160 instruction set architecture (ISA) developed by Hitachi.
161 http://www.hitachi.com/
162 http://en.wikipedia.org/wiki/SuperH
166 depends on BR2_DEPRECATED_SINCE_2015_05
168 SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC)
169 instruction set architecture (ISA) developed by Hitachi.
170 http://www.hitachi.com/
171 http://en.wikipedia.org/wiki/SuperH
176 SPARC (from Scalable Processor Architecture) is a RISC instruction
177 set architecture (ISA) developed by Sun Microsystems.
178 http://www.oracle.com/sun
179 http://en.wikipedia.org/wiki/Sparc
183 select BR2_ARCH_IS_64
185 x86-64 is an extension of the x86 instruction set (Intel i386
186 architecture compatible microprocessor).
187 http://en.wikipedia.org/wiki/X86_64
192 Xtensa is a Tensilica processor IP architecture.
193 http://en.wikipedia.org/wiki/Xtensa
194 http://www.tensilica.com/
198 # The following string values are defined by the individual
199 # Config.in.$ARCH files
206 config BR2_GCC_TARGET_ARCH
209 config BR2_GCC_TARGET_ABI
212 config BR2_GCC_TARGET_CPU
215 config BR2_GCC_TARGET_CPU_REVISION
218 # The value of this option will be passed as --with-fpu=<value> when
219 # building gcc (internal backend) or -mfpu=<value> in the toolchain
220 # wrapper (external toolchain)
221 config BR2_GCC_TARGET_FPU
224 # The value of this option will be passed as --with-float=<value> when
225 # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
226 # wrapper (external toolchain)
227 config BR2_GCC_TARGET_FLOAT_ABI
230 # The value of this option will be passed as --with-mode=<value> when
231 # building gcc (internal backend) or -m<value> in the toolchain
232 # wrapper (external toolchain)
233 config BR2_GCC_TARGET_MODE
236 # If the architecture has atomic operations, select this:
237 config BR2_ARCH_HAS_ATOMICS
240 # Must be selected by binary formats that support shared libraries.
241 config BR2_BINFMT_SUPPORTS_SHARED
244 # Set up target binary format
246 prompt "Target Binary Format"
247 default BR2_BINFMT_ELF if !(BR2_bfin || BR2_m68k)
248 default BR2_BINFMT_FDPIC if BR2_bfin
249 default BR2_BINFMT_FLAT if BR2_m68k
251 config BR2_BINFMT_ELF
253 depends on !BR2_bfin && !BR2_m68k
254 select BR2_BINFMT_SUPPORTS_SHARED
256 ELF (Executable and Linkable Format) is a format for libraries and
257 executables used across different architectures and operating
260 config BR2_BINFMT_FDPIC
263 select BR2_BINFMT_SUPPORTS_SHARED
265 ELF FDPIC binaries are based on ELF, but allow the individual load
266 segments of a binary to be located in memory independently of each
267 other. This makes this format ideal for use in environments where no
270 config BR2_BINFMT_FLAT
272 depends on BR2_bfin || BR2_m68k
274 FLAT binary is a relatively simple and lightweight executable format
275 based on the original a.out format. It is widely used in environment
276 where no MMU is available.
280 # Set up flat binary type
282 prompt "FLAT Binary type"
283 depends on BR2_BINFMT_FLAT
284 default BR2_BINFMT_FLAT_ONE
286 config BR2_BINFMT_FLAT_ONE
287 bool "One memory region"
289 All segments are linked into one memory region.
291 config BR2_BINFMT_FLAT_SEP_DATA
292 bool "Separate data and code region"
294 Allow for the data and text segments to be separated and placed in
295 different regions of memory.
297 config BR2_BINFMT_FLAT_SHARED
299 # Even though this really generates shared binaries, there is no libdl
300 # and dlopen() cannot be used. So packages that require shared
301 # libraries cannot be built. Therefore, we don't select
302 # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
303 # Although this adds -static to the compilation, that's not a problem
304 # because the -mid-shared-library option overrides it.
306 Allow to load and link indiviual FLAT binaries at run time.
310 if BR2_arcle || BR2_arceb
311 source "arch/Config.in.arc"
314 if BR2_arm || BR2_armeb
315 source "arch/Config.in.arm"
319 source "arch/Config.in.aarch64"
323 source "arch/Config.in.bfin"
327 source "arch/Config.in.m68k"
330 if BR2_microblazeel || BR2_microblazebe
331 source "arch/Config.in.microblaze"
334 if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
335 source "arch/Config.in.mips"
339 source "arch/Config.in.nios2"
342 if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
343 source "arch/Config.in.powerpc"
346 if BR2_sh || BR2_sh64
347 source "arch/Config.in.sh"
351 source "arch/Config.in.sparc"
354 if BR2_i386 || BR2_x86_64
355 source "arch/Config.in.x86"
359 source "arch/Config.in.xtensa"
362 endmenu # Target options