1 From d2efc9f3dc62810ef6075f8759c9856016447c14 Mon Sep 17 00:00:00 2001
2 From: Gerd Hoffmann <kraxel@redhat.com>
3 Date: Tue, 4 Sep 2012 14:42:20 +0200
4 Subject: [PATCH] xhci: kill xhci_mem_{read,write} dispatcher functions
6 ... and register subregions instead, so we offload the dispatching
7 to the the memory subsystem which is designed to handle it.
9 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
11 hw/usb/hcd-xhci.c | 140 +++++++++++++++++++++++++++++-------------------------
12 1 file changed, 75 insertions(+), 65 deletions(-)
14 diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
15 index 4992705..4ba9464 100644
16 --- a/hw/usb/hcd-xhci.c
17 +++ b/hw/usb/hcd-xhci.c
18 @@ -404,6 +404,10 @@ struct XHCIState {
22 + MemoryRegion mem_cap;
23 + MemoryRegion mem_oper;
24 + MemoryRegion mem_runtime;
25 + MemoryRegion mem_doorbell;
29 @@ -2343,8 +2347,9 @@ static void xhci_reset(DeviceState *dev)
30 xhci_mfwrap_update(xhci);
33 -static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
34 +static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
36 + XHCIState *xhci = ptr;
40 @@ -2401,7 +2406,7 @@ static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
41 ret = 0x00000000; /* reserved */
44 - fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
45 + fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg);
49 @@ -2482,8 +2487,9 @@ static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
53 -static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
54 +static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size)
56 + XHCIState *xhci = ptr;
60 @@ -2519,7 +2525,7 @@ static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
64 - fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
65 + fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg);
69 @@ -2527,8 +2533,11 @@ static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
73 -static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
74 +static void xhci_oper_write(void *ptr, target_phys_addr_t reg,
75 + uint64_t val, unsigned size)
77 + XHCIState *xhci = ptr;
80 xhci_port_write(xhci, reg - 0x400, val);
82 @@ -2586,12 +2595,14 @@ static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
83 xhci->config = val & 0xff;
86 - fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
87 + fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg);
91 -static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
92 +static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg,
95 + XHCIState *xhci = ptr;
99 @@ -2600,7 +2611,8 @@ static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
100 ret = xhci_mfindex_get(xhci) & 0x3fff;
103 - fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
104 + fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n",
109 @@ -2635,14 +2647,16 @@ static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
113 -static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
114 +static void xhci_runtime_write(void *ptr, target_phys_addr_t reg,
115 + uint64_t val, unsigned size)
117 + XHCIState *xhci = ptr;
118 int v = (reg - 0x20) / 0x20;
119 XHCIInterrupter *intr = &xhci->intr[v];
120 trace_usb_xhci_runtime_write(reg, val);
123 - fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
124 + fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg);
128 @@ -2684,19 +2698,24 @@ static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
129 xhci_events_update(xhci, v);
132 - fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
133 + fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n",
138 -static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
139 +static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg,
142 /* doorbells always read as 0 */
143 trace_usb_xhci_doorbell_read(reg, 0);
147 -static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
148 +static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg,
149 + uint64_t val, unsigned size)
151 + XHCIState *xhci = ptr;
153 trace_usb_xhci_doorbell_write(reg, val);
155 if (!xhci_running(xhci)) {
156 @@ -2710,69 +2729,47 @@ static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
158 xhci_process_commands(xhci);
160 - fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
161 + fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n",
165 if (reg > MAXSLOTS) {
166 - fprintf(stderr, "xhci: bad doorbell %d\n", reg);
167 + fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg);
168 } else if (val > 31) {
169 - fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
170 + fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n",
171 + (int)reg, (uint32_t)val);
173 xhci_kick_ep(xhci, reg, val);
178 -static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
181 - XHCIState *xhci = ptr;
183 - /* Only aligned reads are allowed on xHCI */
185 - fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
189 - if (addr < LEN_CAP) {
190 - return xhci_cap_read(xhci, addr);
191 - } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
192 - return xhci_oper_read(xhci, addr - OFF_OPER);
193 - } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
194 - return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
195 - } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
196 - return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
198 - fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
203 -static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
204 - uint64_t val, unsigned size)
206 - XHCIState *xhci = ptr;
207 +static const MemoryRegionOps xhci_cap_ops = {
208 + .read = xhci_cap_read,
209 + .valid.min_access_size = 4,
210 + .valid.max_access_size = 4,
211 + .endianness = DEVICE_LITTLE_ENDIAN,
214 - /* Only aligned writes are allowed on xHCI */
216 - fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
219 +static const MemoryRegionOps xhci_oper_ops = {
220 + .read = xhci_oper_read,
221 + .write = xhci_oper_write,
222 + .valid.min_access_size = 4,
223 + .valid.max_access_size = 4,
224 + .endianness = DEVICE_LITTLE_ENDIAN,
227 - if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
228 - xhci_oper_write(xhci, addr - OFF_OPER, val);
229 - } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
230 - xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
231 - } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
232 - xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
234 - fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
237 +static const MemoryRegionOps xhci_runtime_ops = {
238 + .read = xhci_runtime_read,
239 + .write = xhci_runtime_write,
240 + .valid.min_access_size = 4,
241 + .valid.max_access_size = 4,
242 + .endianness = DEVICE_LITTLE_ENDIAN,
245 -static const MemoryRegionOps xhci_mem_ops = {
246 - .read = xhci_mem_read,
247 - .write = xhci_mem_write,
248 +static const MemoryRegionOps xhci_doorbell_ops = {
249 + .read = xhci_doorbell_read,
250 + .write = xhci_doorbell_write,
251 .valid.min_access_size = 1,
252 .valid.max_access_size = 4,
253 .impl.min_access_size = 4,
254 @@ -2940,8 +2937,21 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
256 xhci->irq = xhci->pci_dev.irq[0];
258 - memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
260 + memory_region_init(&xhci->mem, "xhci", LEN_REGS);
261 + memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci,
262 + "capabilities", LEN_CAP);
263 + memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci,
264 + "operational", 0x400 + 0x10 * xhci->numports);
265 + memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci,
266 + "runtime", LEN_RUNTIME);
267 + memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci,
268 + "doorbell", LEN_DOORBELL);
270 + memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
271 + memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
272 + memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
273 + memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
275 pci_register_bar(&xhci->pci_dev, 0,
276 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,