1 From cb97f34eca351d150574c724047709b76d00d08a Mon Sep 17 00:00:00 2001
2 From: Francesco Lavra <francescolavra.fl@gmail.com>
3 Date: Wed, 19 Sep 2012 05:51:58 +0000
4 Subject: [PATCH] Versatile Express: Fix NOR flash 0 address and remove flash
7 In the A series memory map (implemented in the Cortex A15 CoreTile), the
8 first NOR flash bank (flash 0) is mapped to address 0x08000000, while
9 address 0x00000000 can be configured as alias to either the first or the
10 second flash bank. This patch fixes the definition of flash 0 address,
11 and for simplicity removes the alias definition.
13 Signed-off-by: Francesco Lavra <francescolavra.fl@gmail.com>
14 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15 (cherry picked from commit 661bafb3e14bfffcb0a7c7910534c7944608ca45)
17 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
19 hw/vexpress.c | 7 ++-----
20 1 file changed, 2 insertions(+), 5 deletions(-)
22 diff --git a/hw/vexpress.c b/hw/vexpress.c
23 index b615844..454c2bb 100644
26 @@ -62,7 +62,6 @@ enum {
34 @@ -104,9 +103,8 @@ static target_phys_addr_t motherboard_legacy_map[] = {
37 static target_phys_addr_t motherboard_aseries_map[] = {
38 - /* CS0: 0x00000000 .. 0x0c000000 */
39 - [VE_NORFLASH0] = 0x00000000,
40 - [VE_NORFLASH0ALIAS] = 0x08000000,
41 + /* CS0: 0x08000000 .. 0x0c000000 */
42 + [VE_NORFLASH0] = 0x08000000,
43 /* CS4: 0x0c000000 .. 0x10000000 */
44 [VE_NORFLASH1] = 0x0c000000,
45 /* CS5: 0x10000000 .. 0x14000000 */
46 @@ -413,7 +411,6 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard,
47 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
49 /* VE_NORFLASH0: not modelled */
50 - /* VE_NORFLASH0ALIAS: not modelled */
51 /* VE_NORFLASH1: not modelled */
53 sram_size = 0x2000000;