1 From 12e60f780a097837840ab1e7bb7d54b8c15112e8 Mon Sep 17 00:00:00 2001
2 From: Richard Henderson <rth@twiddle.net>
3 Date: Sun, 25 Mar 2012 21:36:28 +0200
4 Subject: [PATCH] tcg-sparc: Mask shift immediates to avoid illegal insns.
6 The xtensa-test image generates a sra_i32 with count 0x40.
7 Whether this is accident of tcg constant propagation or
8 originating directly from the instruction stream is immaterial.
10 Signed-off-by: Richard Henderson <rth@twiddle.net>
11 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
13 tcg/sparc/tcg-target.c | 18 ++++++++++++------
14 1 file changed, 12 insertions(+), 6 deletions(-)
16 diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
17 index e625aa3..be5c170 100644
18 --- a/tcg/sparc/tcg-target.c
19 +++ b/tcg/sparc/tcg-target.c
20 @@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
22 case INDEX_op_shl_i32:
26 + /* Limit immediate shift count lest we create an illegal insn. */
27 + tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c);
29 case INDEX_op_shr_i32:
33 case INDEX_op_sar_i32:
37 case INDEX_op_mul_i32:
40 @@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
42 case INDEX_op_shl_i64:
46 + /* Limit immediate shift count lest we create an illegal insn. */
47 + tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c);
49 case INDEX_op_shr_i64:
53 case INDEX_op_sar_i64:
57 case INDEX_op_mul_i64: