1 From 552720cea4c1ca99dd1919cb8a80b6b8f3b13cda Mon Sep 17 00:00:00 2001
2 From: Aurelien Jarno <aurelien@aurel32.net>
3 Date: Fri, 21 Sep 2012 18:20:26 +0200
4 Subject: [PATCH] tcg/mips: implement movcond op on MIPS32R2
6 movcond operation can be implemented on MIPS32 Release 2 using the MOVN,
7 MOVZ, SLT and SLTU instructions.
9 Reviewed-by: Richard Henderson <rth@twiddle.net>
10 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
11 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
13 tcg/mips/tcg-target.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++
14 tcg/mips/tcg-target.h | 8 ++++++
15 2 files changed, 77 insertions(+)
17 diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
18 index b2e1056..c272b38 100644
19 --- a/tcg/mips/tcg-target.c
20 +++ b/tcg/mips/tcg-target.c
21 @@ -308,6 +308,8 @@ enum {
22 OPC_SRAV = OPC_SPECIAL | 0x07,
23 OPC_JR = OPC_SPECIAL | 0x08,
24 OPC_JALR = OPC_SPECIAL | 0x09,
25 + OPC_MOVZ = OPC_SPECIAL | 0x0A,
26 + OPC_MOVN = OPC_SPECIAL | 0x0B,
27 OPC_MFHI = OPC_SPECIAL | 0x10,
28 OPC_MFLO = OPC_SPECIAL | 0x12,
29 OPC_MULT = OPC_SPECIAL | 0x18,
30 @@ -735,6 +737,68 @@ static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGArg arg1,
31 reloc_pc16(label_ptr, (tcg_target_long) s->code_ptr);
34 +static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
35 + TCGArg c1, TCGArg c2, TCGArg v)
40 + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c2);
41 + } else if (c2 == 0) {
42 + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, c1);
44 + tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
45 + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
50 + tcg_out_opc_reg(s, OPC_MOVN, ret, v, c2);
51 + } else if (c2 == 0) {
52 + tcg_out_opc_reg(s, OPC_MOVN, ret, v, c1);
54 + tcg_out_opc_reg(s, OPC_XOR, TCG_REG_AT, c1, c2);
55 + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
59 + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
60 + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
63 + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
64 + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
67 + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c1, c2);
68 + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
71 + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c1, c2);
72 + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
75 + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
76 + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
79 + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
80 + tcg_out_opc_reg(s, OPC_MOVZ, ret, v, TCG_REG_AT);
83 + tcg_out_opc_reg(s, OPC_SLT, TCG_REG_AT, c2, c1);
84 + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
87 + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_AT, c2, c1);
88 + tcg_out_opc_reg(s, OPC_MOVN, ret, v, TCG_REG_AT);
96 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
97 TCGArg arg1, TCGArg arg2)
99 @@ -1468,6 +1532,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
100 tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]);
103 + case INDEX_op_movcond_i32:
104 + tcg_out_movcond(s, args[5], args[0], args[1], args[2], args[3]);
107 case INDEX_op_setcond_i32:
108 tcg_out_setcond(s, args[3], args[0], args[1], args[2]);
110 @@ -1559,6 +1627,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
111 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
113 { INDEX_op_brcond_i32, { "rZ", "rZ" } },
114 + { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
115 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
116 { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
118 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
119 index 897a737..d147e70 100644
120 --- a/tcg/mips/tcg-target.h
121 +++ b/tcg/mips/tcg-target.h
122 @@ -86,7 +86,15 @@ typedef enum {
123 #define TCG_TARGET_HAS_orc_i32 0
124 #define TCG_TARGET_HAS_eqv_i32 0
125 #define TCG_TARGET_HAS_nand_i32 0
127 +/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
128 +#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \
129 + defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \
130 + defined(_MIPS_ARCH_LOONGSON2F)
131 +#define TCG_TARGET_HAS_movcond_i32 1
133 #define TCG_TARGET_HAS_movcond_i32 0
136 /* optional instructions only implemented on MIPS32R2 */
137 #ifdef _MIPS_ARCH_MIPS32R2