0066-tcg-mips-implement-deposit-op-on-MIPS32R2.patch

   1 From 7c3e573b364a65d4abce5266c376f4e77624b039 Mon Sep 17 00:00:00 2001
   2 From: Aurelien Jarno <aurelien@aurel32.net>
   3 Date: Fri, 21 Sep 2012 18:20:26 +0200
   4 Subject: [PATCH] tcg/mips: implement deposit op on MIPS32R2
   5
   6 deposit operations can be optimized on MIPS32 Release 2 using the INS
   7 instruction.
   8
   9 Reviewed-by: Richard Henderson <rth@twiddle.net>
  10 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
  11 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
  12 ---
  13  tcg/mips/tcg-target.c | 8 ++++++++
  14  tcg/mips/tcg-target.h | 3 ++-
  15  2 files changed, 10 insertions(+), 1 deletion(-)
  16
  17 diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
  18 index 592e42a..b2e1056 100644
  19 --- a/tcg/mips/tcg-target.c
  20 +++ b/tcg/mips/tcg-target.c
  21 @@ -328,6 +328,7 @@ enum {
  22      OPC_BGEZ     = OPC_REGIMM | (0x01 << 16),
  23
  24      OPC_SPECIAL3 = 0x1f << 26,
  25 +    OPC_INS      = OPC_SPECIAL3 | 0x004,
  26      OPC_WSBH     = OPC_SPECIAL3 | 0x0a0,
  27      OPC_SEB      = OPC_SPECIAL3 | 0x420,
  28      OPC_SEH      = OPC_SPECIAL3 | 0x620,
  29 @@ -1455,6 +1456,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
  30          tcg_out_ext16s(s, args[0], args[1]);
  31          break;
  32
  33 +    case INDEX_op_deposit_i32:
  34 +        tcg_out_opc_imm(s, OPC_INS, args[0], args[2],
  35 +                        ((args[3] + args[4] - 1) << 11) | (args[3] << 6));
  36 +        break;
  37 +
  38      case INDEX_op_brcond_i32:
  39          tcg_out_brcond(s, args[2], args[0], args[1], args[3]);
  40          break;
  41 @@ -1550,6 +1556,8 @@ static const TCGTargetOpDef mips_op_defs[] = {
  42      { INDEX_op_ext8s_i32, { "r", "rZ" } },
  43      { INDEX_op_ext16s_i32, { "r", "rZ" } },
  44
  45 +    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
  46 +
  47      { INDEX_op_brcond_i32, { "rZ", "rZ" } },
  48      { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
  49      { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
  50 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
  51 index 470314c..897a737 100644
  52 --- a/tcg/mips/tcg-target.h
  53 +++ b/tcg/mips/tcg-target.h
  54 @@ -86,7 +86,6 @@ typedef enum {
  55  #define TCG_TARGET_HAS_orc_i32          0
  56  #define TCG_TARGET_HAS_eqv_i32          0
  57  #define TCG_TARGET_HAS_nand_i32         0
  58 -#define TCG_TARGET_HAS_deposit_i32      0
  59  #define TCG_TARGET_HAS_movcond_i32      0
  60
  61  /* optional instructions only implemented on MIPS32R2 */
  62 @@ -94,10 +93,12 @@ typedef enum {
  63  #define TCG_TARGET_HAS_bswap16_i32      1
  64  #define TCG_TARGET_HAS_bswap32_i32      1
  65  #define TCG_TARGET_HAS_rot_i32          1
  66 +#define TCG_TARGET_HAS_deposit_i32      1
  67  #else
  68  #define TCG_TARGET_HAS_bswap16_i32      0
  69  #define TCG_TARGET_HAS_bswap32_i32      0
  70  #define TCG_TARGET_HAS_rot_i32          0
  71 +#define TCG_TARGET_HAS_deposit_i32      0
  72  #endif
  73
  74  /* optional instructions automatically implemented */
  75 --
  76 1.7.12.1
  77