0047-target-xtensa-fix-extui-shift-amount.patch

   1 From 1c596a9498830485a1b2f4a4445643a149179b99 Mon Sep 17 00:00:00 2001
   2 From: Max Filippov <jcmvbkbc@gmail.com>
   3 Date: Fri, 21 Sep 2012 02:59:49 +0400
   4 Subject: [PATCH] target-xtensa: fix extui shift amount
   5
   6 extui opcode only uses lowermost op1 bit for sa4.
   7
   8 Reported-by: malc <av1474@comtv.ru>
   9 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
  10 Cc: qemu-stable <qemu-stable@nongnu.org>
  11 Signed-off-by: malc <av1474@comtv.ru>
  12 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
  13 ---
  14  target-xtensa/translate.c | 24 +++++++++++++++++++++---
  15  1 file changed, 21 insertions(+), 3 deletions(-)
  16
  17 diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
  18 index 1900bd5..7a1c528 100644
  19 --- a/target-xtensa/translate.c
  20 +++ b/target-xtensa/translate.c
  21 @@ -1778,12 +1778,30 @@ static void disas_xtensa_insn(DisasContext *dc)
  22          case 5:
  23              gen_window_check2(dc, RRR_R, RRR_T);
  24              {
  25 -                int shiftimm = RRR_S | (OP1 << 4);
  26 +                int shiftimm = RRR_S | ((OP1 & 1) << 4);
  27                  int maskimm = (1 << (OP2 + 1)) - 1;
  28
  29                  TCGv_i32 tmp = tcg_temp_new_i32();
  30 -                tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
  31 -                tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
  32 +
  33 +                if (shiftimm) {
  34 +                    tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
  35 +                } else {
  36 +                    tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
  37 +                }
  38 +
  39 +                switch (maskimm) {
  40 +                case 0xff:
  41 +                    tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
  42 +                    break;
  43 +
  44 +                case 0xffff:
  45 +                    tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
  46 +                    break;
  47 +
  48 +                default:
  49 +                    tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
  50 +                    break;
  51 +                }
  52                  tcg_temp_free(tmp);
  53              }
  54              break;
  55 --
  56 1.7.12.1
  57