1 From 5dd8e9207a39d8fe41eaa110edfdba5e37064562 Mon Sep 17 00:00:00 2001
2 From: Richard Henderson <rth@twiddle.net>
3 Date: Tue, 18 Sep 2012 21:55:33 -0700
4 Subject: [PATCH] target-mips: Fix MIPS_DEBUG.
6 The macro uses the DisasContext. Pass it around as needed.
8 Signed-off-by: Richard Henderson <rth@twiddle.net>
9 Acked-by: Aurelien Jarno <aurelien@aurel32.net>
10 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
11 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
13 target-mips/translate.c | 74 +++++++++++++++++++++++++------------------------
14 1 file changed, 38 insertions(+), 36 deletions(-)
16 diff --git a/target-mips/translate.c b/target-mips/translate.c
17 index c31f91c..4937f6b 100644
18 --- a/target-mips/translate.c
19 +++ b/target-mips/translate.c
20 @@ -1431,7 +1431,8 @@ static void gen_arith_imm (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
23 /* Logic with immediate operand */
24 -static void gen_logic_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm)
25 +static void gen_logic_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
26 + int rt, int rs, int16_t imm)
29 const char *opn = "imm logic";
30 @@ -1474,7 +1475,8 @@ static void gen_logic_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int1
33 /* Set on less than with immediate operand */
34 -static void gen_slt_imm (CPUMIPSState *env, uint32_t opc, int rt, int rs, int16_t imm)
35 +static void gen_slt_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
36 + int rt, int rs, int16_t imm)
38 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
39 const char *opn = "imm arith";
40 @@ -1775,7 +1777,8 @@ static void gen_arith (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
43 /* Conditional move */
44 -static void gen_cond_move (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
45 +static void gen_cond_move(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
46 + int rd, int rs, int rt)
48 const char *opn = "cond move";
50 @@ -1813,7 +1816,8 @@ static void gen_cond_move (CPUMIPSState *env, uint32_t opc, int rd, int rs, int
54 -static void gen_logic (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
55 +static void gen_logic(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
56 + int rd, int rs, int rt)
58 const char *opn = "logic";
60 @@ -1874,7 +1878,8 @@ static void gen_logic (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
63 /* Set on lower than */
64 -static void gen_slt (CPUMIPSState *env, uint32_t opc, int rd, int rs, int rt)
65 +static void gen_slt(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
66 + int rd, int rs, int rt)
68 const char *opn = "slt";
70 @@ -8778,10 +8783,10 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
71 gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm);
74 - gen_slt_imm(env, OPC_SLTI, 24, rx, imm);
75 + gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm);
78 - gen_slt_imm(env, OPC_SLTIU, 24, rx, imm);
79 + gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm);
83 @@ -8992,15 +8997,13 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
86 int16_t imm = (uint8_t) ctx->opcode;
88 - gen_slt_imm(env, OPC_SLTI, 24, rx, imm);
89 + gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm);
94 int16_t imm = (uint8_t) ctx->opcode;
96 - gen_slt_imm(env, OPC_SLTIU, 24, rx, imm);
97 + gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm);
101 @@ -9075,8 +9078,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
104 int16_t imm = (uint8_t) ctx->opcode;
106 - gen_logic_imm(env, OPC_XORI, 24, rx, imm);
107 + gen_logic_imm(env, ctx, OPC_XORI, 24, rx, imm);
110 #if defined(TARGET_MIPS64)
111 @@ -9188,10 +9190,10 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
115 - gen_slt(env, OPC_SLT, 24, rx, ry);
116 + gen_slt(env, ctx, OPC_SLT, 24, rx, ry);
119 - gen_slt(env, OPC_SLTU, 24, rx, ry);
120 + gen_slt(env, ctx, OPC_SLTU, 24, rx, ry);
123 generate_exception(ctx, EXCP_BREAK);
124 @@ -9212,22 +9214,22 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx,
128 - gen_logic(env, OPC_XOR, 24, rx, ry);
129 + gen_logic(env, ctx, OPC_XOR, 24, rx, ry);
132 gen_arith(env, ctx, OPC_SUBU, rx, 0, ry);
135 - gen_logic(env, OPC_AND, rx, rx, ry);
136 + gen_logic(env, ctx, OPC_AND, rx, rx, ry);
139 - gen_logic(env, OPC_OR, rx, rx, ry);
140 + gen_logic(env, ctx, OPC_OR, rx, rx, ry);
143 - gen_logic(env, OPC_XOR, rx, rx, ry);
144 + gen_logic(env, ctx, OPC_XOR, rx, rx, ry);
147 - gen_logic(env, OPC_NOR, rx, ry, 0);
148 + gen_logic(env, ctx, OPC_NOR, rx, ry, 0);
151 gen_HILO(ctx, OPC_MFHI, rx);
152 @@ -9849,7 +9851,7 @@ static void gen_andi16 (CPUMIPSState *env, DisasContext *ctx)
153 int rs = mmreg(uMIPS_RS(ctx->opcode));
154 int encoded = ZIMM(ctx->opcode, 0, 4);
156 - gen_logic_imm(env, OPC_ANDI, rd, rs, decoded_imm[encoded]);
157 + gen_logic_imm(env, ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]);
160 static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
161 @@ -9911,25 +9913,25 @@ static void gen_pool16c_insn (CPUMIPSState *env, DisasContext *ctx, int *is_bran
165 - gen_logic(env, OPC_NOR, rd, rs, 0);
166 + gen_logic(env, ctx, OPC_NOR, rd, rs, 0);
172 - gen_logic(env, OPC_XOR, rd, rd, rs);
173 + gen_logic(env, ctx, OPC_XOR, rd, rd, rs);
179 - gen_logic(env, OPC_AND, rd, rd, rs);
180 + gen_logic(env, ctx, OPC_AND, rd, rd, rs);
186 - gen_logic(env, OPC_OR, rd, rd, rs);
187 + gen_logic(env, ctx, OPC_OR, rd, rd, rs);
191 @@ -10743,7 +10745,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
195 - gen_logic(env, mips32_op, rd, rs, rt);
196 + gen_logic(env, ctx, mips32_op, rd, rs, rt);
200 @@ -10752,7 +10754,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
202 mips32_op = OPC_SLTU;
204 - gen_slt(env, mips32_op, rd, rs, rt);
205 + gen_slt(env, ctx, mips32_op, rd, rs, rt);
208 goto pool32a_invalid;
209 @@ -10768,7 +10770,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
211 mips32_op = OPC_MOVZ;
213 - gen_cond_move(env, mips32_op, rd, rs, rt);
214 + gen_cond_move(env, ctx, mips32_op, rd, rs, rt);
217 gen_ldxs(ctx, rs, rt, rd);
218 @@ -11181,7 +11183,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
222 - gen_logic_imm(env, OPC_LUI, rs, -1, imm);
223 + gen_logic_imm(env, ctx, OPC_LUI, rs, -1, imm);
227 @@ -11300,7 +11302,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
229 mips32_op = OPC_ANDI;
231 - gen_logic_imm(env, mips32_op, rt, rs, imm);
232 + gen_logic_imm(env, ctx, mips32_op, rt, rs, imm);
235 /* Set less than immediate */
236 @@ -11310,7 +11312,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
238 mips32_op = OPC_SLTIU;
240 - gen_slt_imm(env, mips32_op, rt, rs, imm);
241 + gen_slt_imm(env, ctx, mips32_op, rt, rs, imm);
244 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
245 @@ -11787,7 +11789,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
247 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32 |
248 INSN_LOONGSON2E | INSN_LOONGSON2F);
249 - gen_cond_move(env, op1, rd, rs, rt);
250 + gen_cond_move(env, ctx, op1, rd, rs, rt);
252 case OPC_ADD ... OPC_SUBU:
253 gen_arith(env, ctx, op1, rd, rs, rt);
254 @@ -11814,13 +11816,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
256 case OPC_SLT: /* Set on less than */
258 - gen_slt(env, op1, rd, rs, rt);
259 + gen_slt(env, ctx, op1, rd, rs, rt);
261 case OPC_AND: /* Logic*/
265 - gen_logic(env, op1, rd, rs, rt);
266 + gen_logic(env, ctx, op1, rd, rs, rt);
268 case OPC_MULT ... OPC_DIVU:
270 @@ -12221,13 +12223,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
272 case OPC_SLTI: /* Set on less than with immediate opcode */
274 - gen_slt_imm(env, op, rt, rs, imm);
275 + gen_slt_imm(env, ctx, op, rt, rs, imm);
277 case OPC_ANDI: /* Arithmetic with immediate opcode */
281 - gen_logic_imm(env, op, rt, rs, imm);
282 + gen_logic_imm(env, ctx, op, rt, rs, imm);
284 case OPC_J ... OPC_JAL: /* Jump */
285 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;