1 From 28b8f097f9fb107882aa51bd25ba87619beb033e Mon Sep 17 00:00:00 2001
2 From: Blue Swirl <blauwirbel@gmail.com>
3 Date: Tue, 4 Sep 2012 20:25:59 +0000
4 Subject: [PATCH] target-arm: final conversion to AREG0 free mode
6 Convert code load functions and switch to AREG0 free mode.
8 Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
9 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
13 target-arm/Makefile.objs | 2 --
14 target-arm/cpu.h | 10 ++++++----
15 target-arm/helper.c | 9 +++++----
16 target-arm/op_helper.c | 8 +-------
17 target-arm/translate.c | 6 +++---
18 6 files changed, 16 insertions(+), 21 deletions(-)
20 diff --git a/configure b/configure
21 index a8827ba..e8806f0 100755
24 @@ -3839,7 +3839,7 @@ symlink "$source_path/Makefile.target" "$target_dir/Makefile"
27 case "$target_arch2" in
28 - alpha | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
29 + alpha | arm* | i386 | lm32 | m68k | or32 | s390x | sparc* | unicore32 | x86_64 | xtensa* | ppc*)
30 echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
33 diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
34 index f447c4f..b6f1a9e 100644
35 --- a/target-arm/Makefile.objs
36 +++ b/target-arm/Makefile.objs
37 @@ -2,5 +2,3 @@ obj-y += arm-semi.o
38 obj-$(CONFIG_SOFTMMU) += machine.o
39 obj-y += translate.o op_helper.o helper.o cpu.o
40 obj-y += neon_helper.o iwmmxt_helper.o
42 -$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
43 diff --git a/target-arm/cpu.h b/target-arm/cpu.h
44 index d7f93d9..7fac94f 100644
45 --- a/target-arm/cpu.h
46 +++ b/target-arm/cpu.h
47 @@ -734,9 +734,10 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
50 /* Load an instruction and return it in the standard little-endian order */
51 -static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
52 +static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
55 - uint32_t insn = ldl_code(addr);
56 + uint32_t insn = cpu_ldl_code(env, addr);
60 @@ -744,9 +745,10 @@ static inline uint32_t arm_ldl_code(uint32_t addr, bool do_swap)
63 /* Ditto, for a halfword (Thumb) instruction */
64 -static inline uint16_t arm_lduw_code(uint32_t addr, bool do_swap)
65 +static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
68 - uint16_t insn = lduw_code(addr);
69 + uint16_t insn = cpu_lduw_code(env, addr);
73 diff --git a/target-arm/helper.c b/target-arm/helper.c
74 index e27df96..58340bd 100644
75 --- a/target-arm/helper.c
76 +++ b/target-arm/helper.c
77 @@ -1756,7 +1756,7 @@ static void do_interrupt_v7m(CPUARMState *env)
79 if (semihosting_enabled) {
81 - nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
82 + nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
85 env->regs[0] = do_arm_semihosting(env);
86 @@ -1828,9 +1828,10 @@ void do_interrupt(CPUARMState *env)
87 if (semihosting_enabled) {
88 /* Check for semihosting interrupt. */
90 - mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
91 + mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
94 - mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
95 + mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
98 /* Only intercept calls from privileged modes, to provide some
99 @@ -1851,7 +1852,7 @@ void do_interrupt(CPUARMState *env)
101 /* See if this is a semihosting syscall. */
102 if (env->thumb && semihosting_enabled) {
103 - mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
104 + mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
106 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
108 diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
109 index 5b868bf..f13fc3a 100644
110 --- a/target-arm/op_helper.c
111 +++ b/target-arm/op_helper.c
113 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
116 -#include "dyngen-exec.h"
119 #define SIGNBIT (uint32_t)0x80000000
120 @@ -72,16 +71,12 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
121 /* try to fill the TLB and return an exception if error. If retaddr is
122 NULL, it means that the function was called in C code (i.e. not
123 from generated code or from helper.c) */
124 -/* XXX: fix it to restore all registers */
125 -void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
126 +void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
129 TranslationBlock *tb;
130 - CPUARMState *saved_env;
135 ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
138 @@ -95,7 +90,6 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
140 raise_exception(env, env->exception_index);
146 diff --git a/target-arm/translate.c b/target-arm/translate.c
147 index 9ae3b26..f4b447a 100644
148 --- a/target-arm/translate.c
149 +++ b/target-arm/translate.c
150 @@ -6534,7 +6534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
154 - insn = arm_ldl_code(s->pc, s->bswap_code);
155 + insn = arm_ldl_code(env, s->pc, s->bswap_code);
158 /* M variants do not implement ARM mode. */
159 @@ -7962,7 +7962,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
160 /* Fall through to 32-bit decode. */
163 - insn = arm_lduw_code(s->pc, s->bswap_code);
164 + insn = arm_lduw_code(env, s->pc, s->bswap_code);
166 insn |= (uint32_t)insn_hw1 << 16;
168 @@ -8992,7 +8992,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
172 - insn = arm_lduw_code(s->pc, s->bswap_code);
173 + insn = arm_lduw_code(env, s->pc, s->bswap_code);
176 switch (insn >> 12) {