0032-target-arm-convert-remaining-helpers.patch

   1 From 18e713cf6b5ae2e7c48bb412c959c10322bef5e5 Mon Sep 17 00:00:00 2001
   2 From: Blue Swirl <blauwirbel@gmail.com>
   3 Date: Tue, 4 Sep 2012 20:19:15 +0000
   4 Subject: [PATCH] target-arm: convert remaining helpers
   5
   6 Convert remaining helpers to AREG0 free mode: add an explicit
   7 CPUState parameter instead of relying on AREG0.
   8
   9 Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
  10 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
  11 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
  12 ---
  13  target-arm/helper.h    |  52 +++++++++----------
  14  target-arm/op_helper.c |  64 +++++++++++------------
  15  target-arm/translate.c | 134 ++++++++++++++++++++++++-------------------------
  16  3 files changed, 125 insertions(+), 125 deletions(-)
  17
  18 diff --git a/target-arm/helper.h b/target-arm/helper.h
  19 index 106aacd..afdb2b5 100644
  20 --- a/target-arm/helper.h
  21 +++ b/target-arm/helper.h
  22 @@ -4,12 +4,12 @@ DEF_HELPER_1(clz, i32, i32)
  23  DEF_HELPER_1(sxtb16, i32, i32)
  24  DEF_HELPER_1(uxtb16, i32, i32)
  25
  26 -DEF_HELPER_2(add_setq, i32, i32, i32)
  27 -DEF_HELPER_2(add_saturate, i32, i32, i32)
  28 -DEF_HELPER_2(sub_saturate, i32, i32, i32)
  29 -DEF_HELPER_2(add_usaturate, i32, i32, i32)
  30 -DEF_HELPER_2(sub_usaturate, i32, i32, i32)
  31 -DEF_HELPER_1(double_saturate, i32, s32)
  32 +DEF_HELPER_3(add_setq, i32, env, i32, i32)
  33 +DEF_HELPER_3(add_saturate, i32, env, i32, i32)
  34 +DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
  35 +DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
  36 +DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
  37 +DEF_HELPER_2(double_saturate, i32, env, s32)
  38  DEF_HELPER_2(sdiv, s32, s32, s32)
  39  DEF_HELPER_2(udiv, i32, i32, i32)
  40  DEF_HELPER_1(rbit, i32, i32)
  41 @@ -40,10 +40,10 @@ PAS_OP(uq)
  42  PAS_OP(uh)
  43  #undef PAS_OP
  44
  45 -DEF_HELPER_2(ssat, i32, i32, i32)
  46 -DEF_HELPER_2(usat, i32, i32, i32)
  47 -DEF_HELPER_2(ssat16, i32, i32, i32)
  48 -DEF_HELPER_2(usat16, i32, i32, i32)
  49 +DEF_HELPER_3(ssat, i32, env, i32, i32)
  50 +DEF_HELPER_3(usat, i32, env, i32, i32)
  51 +DEF_HELPER_3(ssat16, i32, env, i32, i32)
  52 +DEF_HELPER_3(usat16, i32, env, i32, i32)
  53
  54  DEF_HELPER_2(usad8, i32, i32, i32)
  55
  56 @@ -54,7 +54,7 @@ DEF_HELPER_2(exception, void, env, i32)
  57  DEF_HELPER_1(wfi, void, env)
  58
  59  DEF_HELPER_3(cpsr_write, void, env, i32, i32)
  60 -DEF_HELPER_0(cpsr_read, i32)
  61 +DEF_HELPER_1(cpsr_read, i32, env)
  62
  63  DEF_HELPER_3(v7m_msr, void, env, i32, i32)
  64  DEF_HELPER_2(v7m_mrs, i32, env, i32)
  65 @@ -67,7 +67,7 @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
  66  DEF_HELPER_2(get_r13_banked, i32, env, i32)
  67  DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
  68
  69 -DEF_HELPER_1(get_user_reg, i32, i32)
  70 +DEF_HELPER_2(get_user_reg, i32, env, i32)
  71  DEF_HELPER_3(set_user_reg, void, env, i32, i32)
  72
  73  DEF_HELPER_1(vfp_get_fpscr, i32, env)
  74 @@ -140,20 +140,20 @@ DEF_HELPER_2(recpe_f32, f32, f32, env)
  75  DEF_HELPER_2(rsqrte_f32, f32, f32, env)
  76  DEF_HELPER_2(recpe_u32, i32, i32, env)
  77  DEF_HELPER_2(rsqrte_u32, i32, i32, env)
  78 -DEF_HELPER_4(neon_tbl, i32, i32, i32, i32, i32)
  79 -
  80 -DEF_HELPER_2(add_cc, i32, i32, i32)
  81 -DEF_HELPER_2(adc_cc, i32, i32, i32)
  82 -DEF_HELPER_2(sub_cc, i32, i32, i32)
  83 -DEF_HELPER_2(sbc_cc, i32, i32, i32)
  84 -
  85 -DEF_HELPER_2(shl, i32, i32, i32)
  86 -DEF_HELPER_2(shr, i32, i32, i32)
  87 -DEF_HELPER_2(sar, i32, i32, i32)
  88 -DEF_HELPER_2(shl_cc, i32, i32, i32)
  89 -DEF_HELPER_2(shr_cc, i32, i32, i32)
  90 -DEF_HELPER_2(sar_cc, i32, i32, i32)
  91 -DEF_HELPER_2(ror_cc, i32, i32, i32)
  92 +DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32)
  93 +
  94 +DEF_HELPER_3(add_cc, i32, env, i32, i32)
  95 +DEF_HELPER_3(adc_cc, i32, env, i32, i32)
  96 +DEF_HELPER_3(sub_cc, i32, env, i32, i32)
  97 +DEF_HELPER_3(sbc_cc, i32, env, i32, i32)
  98 +
  99 +DEF_HELPER_3(shl, i32, env, i32, i32)
 100 +DEF_HELPER_3(shr, i32, env, i32, i32)
 101 +DEF_HELPER_3(sar, i32, env, i32, i32)
 102 +DEF_HELPER_3(shl_cc, i32, env, i32, i32)
 103 +DEF_HELPER_3(shr_cc, i32, env, i32, i32)
 104 +DEF_HELPER_3(sar_cc, i32, env, i32, i32)
 105 +DEF_HELPER_3(ror_cc, i32, env, i32, i32)
 106
 107  /* neon_helper.c */
 108  DEF_HELPER_3(neon_qadd_u8, i32, env, i32, i32)
 109 diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
 110 index b1adce3..5b868bf 100644
 111 --- a/target-arm/op_helper.c
 112 +++ b/target-arm/op_helper.c
 113 @@ -29,7 +29,7 @@ static void raise_exception(CPUARMState *env, int tt)
 114      cpu_loop_exit(env);
 115  }
 116
 117 -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
 118 +uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
 119                            uint32_t rn, uint32_t maxindex)
 120  {
 121      uint32_t val;
 122 @@ -101,7 +101,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
 123
 124  /* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
 125     instructions into helper.c  */
 126 -uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
 127 +uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
 128  {
 129      uint32_t res = a + b;
 130      if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
 131 @@ -109,7 +109,7 @@ uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
 132      return res;
 133  }
 134
 135 -uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
 136 +uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 137  {
 138      uint32_t res = a + b;
 139      if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
 140 @@ -119,7 +119,7 @@ uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
 141      return res;
 142  }
 143
 144 -uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
 145 +uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 146  {
 147      uint32_t res = a - b;
 148      if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 149 @@ -129,7 +129,7 @@ uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
 150      return res;
 151  }
 152
 153 -uint32_t HELPER(double_saturate)(int32_t val)
 154 +uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 155  {
 156      uint32_t res;
 157      if (val >= 0x40000000) {
 158 @@ -144,7 +144,7 @@ uint32_t HELPER(double_saturate)(int32_t val)
 159      return res;
 160  }
 161
 162 -uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
 163 +uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 164  {
 165      uint32_t res = a + b;
 166      if (res < a) {
 167 @@ -154,7 +154,7 @@ uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
 168      return res;
 169  }
 170
 171 -uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
 172 +uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 173  {
 174      uint32_t res = a - b;
 175      if (res > a) {
 176 @@ -165,7 +165,7 @@ uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
 177  }
 178
 179  /* Signed saturation.  */
 180 -static inline uint32_t do_ssat(int32_t val, int shift)
 181 +static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 182  {
 183      int32_t top;
 184      uint32_t mask;
 185 @@ -183,7 +183,7 @@ static inline uint32_t do_ssat(int32_t val, int shift)
 186  }
 187
 188  /* Unsigned saturation.  */
 189 -static inline uint32_t do_usat(int32_t val, int shift)
 190 +static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 191  {
 192      uint32_t max;
 193
 194 @@ -199,34 +199,34 @@ static inline uint32_t do_usat(int32_t val, int shift)
 195  }
 196
 197  /* Signed saturate.  */
 198 -uint32_t HELPER(ssat)(uint32_t x, uint32_t shift)
 199 +uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 200  {
 201 -    return do_ssat(x, shift);
 202 +    return do_ssat(env, x, shift);
 203  }
 204
 205  /* Dual halfword signed saturate.  */
 206 -uint32_t HELPER(ssat16)(uint32_t x, uint32_t shift)
 207 +uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 208  {
 209      uint32_t res;
 210
 211 -    res = (uint16_t)do_ssat((int16_t)x, shift);
 212 -    res |= do_ssat(((int32_t)x) >> 16, shift) << 16;
 213 +    res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 214 +    res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 215      return res;
 216  }
 217
 218  /* Unsigned saturate.  */
 219 -uint32_t HELPER(usat)(uint32_t x, uint32_t shift)
 220 +uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 221  {
 222 -    return do_usat(x, shift);
 223 +    return do_usat(env, x, shift);
 224  }
 225
 226  /* Dual halfword unsigned saturate.  */
 227 -uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
 228 +uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 229  {
 230      uint32_t res;
 231
 232 -    res = (uint16_t)do_usat((int16_t)x, shift);
 233 -    res |= do_usat(((int32_t)x) >> 16, shift) << 16;
 234 +    res = (uint16_t)do_usat(env, (int16_t)x, shift);
 235 +    res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 236      return res;
 237  }
 238
 239 @@ -243,7 +243,7 @@ void HELPER(exception)(CPUARMState *env, uint32_t excp)
 240      cpu_loop_exit(env);
 241  }
 242
 243 -uint32_t HELPER(cpsr_read)(void)
 244 +uint32_t HELPER(cpsr_read)(CPUARMState *env)
 245  {
 246      return cpsr_read(env) & ~CPSR_EXEC;
 247  }
 248 @@ -254,7 +254,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 249  }
 250
 251  /* Access to user mode registers from privileged modes.  */
 252 -uint32_t HELPER(get_user_reg)(uint32_t regno)
 253 +uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 254  {
 255      uint32_t val;
 256
 257 @@ -329,7 +329,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 258     The only way to do that in TCG is a conditional branch, which clobbers
 259     all our temporaries.  For now implement these as helper functions.  */
 260
 261 -uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
 262 +uint32_t HELPER (add_cc)(CPUARMState *env, uint32_t a, uint32_t b)
 263  {
 264      uint32_t result;
 265      result = a + b;
 266 @@ -339,7 +339,7 @@ uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
 267      return result;
 268  }
 269
 270 -uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
 271 +uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
 272  {
 273      uint32_t result;
 274      if (!env->CF) {
 275 @@ -354,7 +354,7 @@ uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
 276      return result;
 277  }
 278
 279 -uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
 280 +uint32_t HELPER(sub_cc)(CPUARMState *env, uint32_t a, uint32_t b)
 281  {
 282      uint32_t result;
 283      result = a - b;
 284 @@ -364,7 +364,7 @@ uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
 285      return result;
 286  }
 287
 288 -uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
 289 +uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
 290  {
 291      uint32_t result;
 292      if (!env->CF) {
 293 @@ -381,7 +381,7 @@ uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
 294
 295  /* Similarly for variable shift instructions.  */
 296
 297 -uint32_t HELPER(shl)(uint32_t x, uint32_t i)
 298 +uint32_t HELPER(shl)(CPUARMState *env, uint32_t x, uint32_t i)
 299  {
 300      int shift = i & 0xff;
 301      if (shift >= 32)
 302 @@ -389,7 +389,7 @@ uint32_t HELPER(shl)(uint32_t x, uint32_t i)
 303      return x << shift;
 304  }
 305
 306 -uint32_t HELPER(shr)(uint32_t x, uint32_t i)
 307 +uint32_t HELPER(shr)(CPUARMState *env, uint32_t x, uint32_t i)
 308  {
 309      int shift = i & 0xff;
 310      if (shift >= 32)
 311 @@ -397,7 +397,7 @@ uint32_t HELPER(shr)(uint32_t x, uint32_t i)
 312      return (uint32_t)x >> shift;
 313  }
 314
 315 -uint32_t HELPER(sar)(uint32_t x, uint32_t i)
 316 +uint32_t HELPER(sar)(CPUARMState *env, uint32_t x, uint32_t i)
 317  {
 318      int shift = i & 0xff;
 319      if (shift >= 32)
 320 @@ -405,7 +405,7 @@ uint32_t HELPER(sar)(uint32_t x, uint32_t i)
 321      return (int32_t)x >> shift;
 322  }
 323
 324 -uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
 325 +uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 326  {
 327      int shift = i & 0xff;
 328      if (shift >= 32) {
 329 @@ -421,7 +421,7 @@ uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
 330      return x;
 331  }
 332
 333 -uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
 334 +uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 335  {
 336      int shift = i & 0xff;
 337      if (shift >= 32) {
 338 @@ -437,7 +437,7 @@ uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
 339      return x;
 340  }
 341
 342 -uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
 343 +uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 344  {
 345      int shift = i & 0xff;
 346      if (shift >= 32) {
 347 @@ -450,7 +450,7 @@ uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
 348      return x;
 349  }
 350
 351 -uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
 352 +uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 353  {
 354      int shift1, shift;
 355      shift1 = i & 0xff;
 356 diff --git a/target-arm/translate.c b/target-arm/translate.c
 357 index 6f651d9..9ae3b26 100644
 358 --- a/target-arm/translate.c
 359 +++ b/target-arm/translate.c
 360 @@ -490,16 +490,16 @@ static inline void gen_arm_shift_reg(TCGv var, int shiftop,
 361  {
 362      if (flags) {
 363          switch (shiftop) {
 364 -        case 0: gen_helper_shl_cc(var, var, shift); break;
 365 -        case 1: gen_helper_shr_cc(var, var, shift); break;
 366 -        case 2: gen_helper_sar_cc(var, var, shift); break;
 367 -        case 3: gen_helper_ror_cc(var, var, shift); break;
 368 +        case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break;
 369 +        case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break;
 370 +        case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break;
 371 +        case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break;
 372          }
 373      } else {
 374          switch (shiftop) {
 375 -        case 0: gen_helper_shl(var, var, shift); break;
 376 -        case 1: gen_helper_shr(var, var, shift); break;
 377 -        case 2: gen_helper_sar(var, var, shift); break;
 378 +        case 0: gen_helper_shl(var, cpu_env, var, shift); break;
 379 +        case 1: gen_helper_shr(var, cpu_env, var, shift); break;
 380 +        case 2: gen_helper_sar(var, cpu_env, var, shift); break;
 381          case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
 382                  tcg_gen_rotr_i32(var, var, shift); break;
 383          }
 384 @@ -6121,7 +6121,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
 385                  tmp2 = neon_load_reg(rm, 0);
 386                  tmp4 = tcg_const_i32(rn);
 387                  tmp5 = tcg_const_i32(n);
 388 -                gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
 389 +                gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5);
 390                  tcg_temp_free_i32(tmp);
 391                  if (insn & (1 << 6)) {
 392                      tmp = neon_load_reg(rd, 1);
 393 @@ -6130,7 +6130,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
 394                      tcg_gen_movi_i32(tmp, 0);
 395                  }
 396                  tmp3 = neon_load_reg(rm, 1);
 397 -                gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
 398 +                gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5);
 399                  tcg_temp_free_i32(tmp5);
 400                  tcg_temp_free_i32(tmp4);
 401                  neon_store_reg(rd, 0, tmp2);
 402 @@ -6818,7 +6818,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 403                      tmp = load_cpu_field(spsr);
 404                  } else {
 405                      tmp = tcg_temp_new_i32();
 406 -                    gen_helper_cpsr_read(tmp);
 407 +                    gen_helper_cpsr_read(tmp, cpu_env);
 408                  }
 409                  store_reg(s, rd, tmp);
 410              }
 411 @@ -6869,11 +6869,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 412              tmp = load_reg(s, rm);
 413              tmp2 = load_reg(s, rn);
 414              if (op1 & 2)
 415 -                gen_helper_double_saturate(tmp2, tmp2);
 416 +                gen_helper_double_saturate(tmp2, cpu_env, tmp2);
 417              if (op1 & 1)
 418 -                gen_helper_sub_saturate(tmp, tmp, tmp2);
 419 +                gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
 420              else
 421 -                gen_helper_add_saturate(tmp, tmp, tmp2);
 422 +                gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
 423              tcg_temp_free_i32(tmp2);
 424              store_reg(s, rd, tmp);
 425              break;
 426 @@ -6911,7 +6911,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 427                  tcg_temp_free_i64(tmp64);
 428                  if ((sh & 2) == 0) {
 429                      tmp2 = load_reg(s, rn);
 430 -                    gen_helper_add_setq(tmp, tmp, tmp2);
 431 +                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 432                      tcg_temp_free_i32(tmp2);
 433                  }
 434                  store_reg(s, rd, tmp);
 435 @@ -6931,7 +6931,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 436                  } else {
 437                      if (op1 == 0) {
 438                          tmp2 = load_reg(s, rn);
 439 -                        gen_helper_add_setq(tmp, tmp, tmp2);
 440 +                        gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 441                          tcg_temp_free_i32(tmp2);
 442                      }
 443                      store_reg(s, rd, tmp);
 444 @@ -7005,11 +7005,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 445                  if (IS_USER(s)) {
 446                      goto illegal_op;
 447                  }
 448 -                gen_helper_sub_cc(tmp, tmp, tmp2);
 449 +                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 450                  gen_exception_return(s, tmp);
 451              } else {
 452                  if (set_cc) {
 453 -                    gen_helper_sub_cc(tmp, tmp, tmp2);
 454 +                    gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 455                  } else {
 456                      tcg_gen_sub_i32(tmp, tmp, tmp2);
 457                  }
 458 @@ -7018,7 +7018,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 459              break;
 460          case 0x03:
 461              if (set_cc) {
 462 -                gen_helper_sub_cc(tmp, tmp2, tmp);
 463 +                gen_helper_sub_cc(tmp, cpu_env, tmp2, tmp);
 464              } else {
 465                  tcg_gen_sub_i32(tmp, tmp2, tmp);
 466              }
 467 @@ -7026,7 +7026,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 468              break;
 469          case 0x04:
 470              if (set_cc) {
 471 -                gen_helper_add_cc(tmp, tmp, tmp2);
 472 +                gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
 473              } else {
 474                  tcg_gen_add_i32(tmp, tmp, tmp2);
 475              }
 476 @@ -7034,7 +7034,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 477              break;
 478          case 0x05:
 479              if (set_cc) {
 480 -                gen_helper_adc_cc(tmp, tmp, tmp2);
 481 +                gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
 482              } else {
 483                  gen_add_carry(tmp, tmp, tmp2);
 484              }
 485 @@ -7042,7 +7042,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 486              break;
 487          case 0x06:
 488              if (set_cc) {
 489 -                gen_helper_sbc_cc(tmp, tmp, tmp2);
 490 +                gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
 491              } else {
 492                  gen_sub_carry(tmp, tmp, tmp2);
 493              }
 494 @@ -7050,7 +7050,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 495              break;
 496          case 0x07:
 497              if (set_cc) {
 498 -                gen_helper_sbc_cc(tmp, tmp2, tmp);
 499 +                gen_helper_sbc_cc(tmp, cpu_env, tmp2, tmp);
 500              } else {
 501                  gen_sub_carry(tmp, tmp2, tmp);
 502              }
 503 @@ -7072,13 +7072,13 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 504              break;
 505          case 0x0a:
 506              if (set_cc) {
 507 -                gen_helper_sub_cc(tmp, tmp, tmp2);
 508 +                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 509              }
 510              tcg_temp_free_i32(tmp);
 511              break;
 512          case 0x0b:
 513              if (set_cc) {
 514 -                gen_helper_add_cc(tmp, tmp, tmp2);
 515 +                gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
 516              }
 517              tcg_temp_free_i32(tmp);
 518              break;
 519 @@ -7395,9 +7395,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 520                          sh = (insn >> 16) & 0x1f;
 521                          tmp2 = tcg_const_i32(sh);
 522                          if (insn & (1 << 22))
 523 -                          gen_helper_usat(tmp, tmp, tmp2);
 524 +                          gen_helper_usat(tmp, cpu_env, tmp, tmp2);
 525                          else
 526 -                          gen_helper_ssat(tmp, tmp, tmp2);
 527 +                          gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
 528                          tcg_temp_free_i32(tmp2);
 529                          store_reg(s, rd, tmp);
 530                      } else if ((insn & 0x00300fe0) == 0x00200f20) {
 531 @@ -7406,9 +7406,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 532                          sh = (insn >> 16) & 0x1f;
 533                          tmp2 = tcg_const_i32(sh);
 534                          if (insn & (1 << 22))
 535 -                          gen_helper_usat16(tmp, tmp, tmp2);
 536 +                          gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
 537                          else
 538 -                          gen_helper_ssat16(tmp, tmp, tmp2);
 539 +                          gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
 540                          tcg_temp_free_i32(tmp2);
 541                          store_reg(s, rd, tmp);
 542                      } else if ((insn & 0x00700fe0) == 0x00000fa0) {
 543 @@ -7518,7 +7518,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 544                               * however it may overflow considered as a signed
 545                               * operation, in which case we must set the Q flag.
 546                               */
 547 -                            gen_helper_add_setq(tmp, tmp, tmp2);
 548 +                            gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 549                          }
 550                          tcg_temp_free_i32(tmp2);
 551                          if (insn & (1 << 22)) {
 552 @@ -7534,7 +7534,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 553                              if (rd != 15)
 554                                {
 555                                  tmp2 = load_reg(s, rd);
 556 -                                gen_helper_add_setq(tmp, tmp, tmp2);
 557 +                                gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 558                                  tcg_temp_free_i32(tmp2);
 559                                }
 560                              store_reg(s, rn, tmp);
 561 @@ -7738,7 +7738,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
 562                              } else if (user) {
 563                                  tmp = tcg_temp_new_i32();
 564                                  tmp2 = tcg_const_i32(i);
 565 -                                gen_helper_get_user_reg(tmp, tmp2);
 566 +                                gen_helper_get_user_reg(tmp, cpu_env, tmp2);
 567                                  tcg_temp_free_i32(tmp2);
 568                              } else {
 569                                  tmp = load_reg(s, i);
 570 @@ -7865,31 +7865,31 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG
 571          break;
 572      case 8: /* add */
 573          if (conds)
 574 -            gen_helper_add_cc(t0, t0, t1);
 575 +            gen_helper_add_cc(t0, cpu_env, t0, t1);
 576          else
 577              tcg_gen_add_i32(t0, t0, t1);
 578          break;
 579      case 10: /* adc */
 580          if (conds)
 581 -            gen_helper_adc_cc(t0, t0, t1);
 582 +            gen_helper_adc_cc(t0, cpu_env, t0, t1);
 583          else
 584              gen_adc(t0, t1);
 585          break;
 586      case 11: /* sbc */
 587          if (conds)
 588 -            gen_helper_sbc_cc(t0, t0, t1);
 589 +            gen_helper_sbc_cc(t0, cpu_env, t0, t1);
 590          else
 591              gen_sub_carry(t0, t0, t1);
 592          break;
 593      case 13: /* sub */
 594          if (conds)
 595 -            gen_helper_sub_cc(t0, t0, t1);
 596 +            gen_helper_sub_cc(t0, cpu_env, t0, t1);
 597          else
 598              tcg_gen_sub_i32(t0, t0, t1);
 599          break;
 600      case 14: /* rsb */
 601          if (conds)
 602 -            gen_helper_sub_cc(t0, t1, t0);
 603 +            gen_helper_sub_cc(t0, cpu_env, t1, t0);
 604          else
 605              tcg_gen_sub_i32(t0, t1, t0);
 606          break;
 607 @@ -8111,7 +8111,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
 608                      gen_st32(tmp, addr, 0);
 609                      tcg_gen_addi_i32(addr, addr, 4);
 610                      tmp = tcg_temp_new_i32();
 611 -                    gen_helper_cpsr_read(tmp);
 612 +                    gen_helper_cpsr_read(tmp, cpu_env);
 613                      gen_st32(tmp, addr, 0);
 614                      if (insn & (1 << 21)) {
 615                          if ((insn & (1 << 24)) == 0) {
 616 @@ -8293,11 +8293,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
 617                  tmp = load_reg(s, rn);
 618                  tmp2 = load_reg(s, rm);
 619                  if (op & 1)
 620 -                    gen_helper_double_saturate(tmp, tmp);
 621 +                    gen_helper_double_saturate(tmp, cpu_env, tmp);
 622                  if (op & 2)
 623 -                    gen_helper_sub_saturate(tmp, tmp2, tmp);
 624 +                    gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
 625                  else
 626 -                    gen_helper_add_saturate(tmp, tmp, tmp2);
 627 +                    gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2);
 628                  tcg_temp_free_i32(tmp2);
 629              } else {
 630                  tmp = load_reg(s, rn);
 631 @@ -8353,7 +8353,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
 632                  tcg_temp_free_i32(tmp2);
 633                  if (rs != 15) {
 634                      tmp2 = load_reg(s, rs);
 635 -                    gen_helper_add_setq(tmp, tmp, tmp2);
 636 +                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 637                      tcg_temp_free_i32(tmp2);
 638                  }
 639                  break;
 640 @@ -8370,13 +8370,13 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
 641                       * however it may overflow considered as a signed
 642                       * operation, in which case we must set the Q flag.
 643                       */
 644 -                    gen_helper_add_setq(tmp, tmp, tmp2);
 645 +                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 646                  }
 647                  tcg_temp_free_i32(tmp2);
 648                  if (rs != 15)
 649                    {
 650                      tmp2 = load_reg(s, rs);
 651 -                    gen_helper_add_setq(tmp, tmp, tmp2);
 652 +                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 653                      tcg_temp_free_i32(tmp2);
 654                    }
 655                  break;
 656 @@ -8393,7 +8393,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
 657                  if (rs != 15)
 658                    {
 659                      tmp2 = load_reg(s, rs);
 660 -                    gen_helper_add_setq(tmp, tmp, tmp2);
 661 +                    gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
 662                      tcg_temp_free_i32(tmp2);
 663                    }
 664                  break;
 665 @@ -8632,7 +8632,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
 666                              gen_helper_v7m_mrs(tmp, cpu_env, addr);
 667                              tcg_temp_free_i32(addr);
 668                          } else {
 669 -                            gen_helper_cpsr_read(tmp);
 670 +                            gen_helper_cpsr_read(tmp, cpu_env);
 671                          }
 672                          store_reg(s, rd, tmp);
 673                          break;
 674 @@ -8721,15 +8721,15 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
 675                          if (op & 4) {
 676                              /* Unsigned.  */
 677                              if ((op & 1) && shift == 0)
 678 -                                gen_helper_usat16(tmp, tmp, tmp2);
 679 +                                gen_helper_usat16(tmp, cpu_env, tmp, tmp2);
 680                              else
 681 -                                gen_helper_usat(tmp, tmp, tmp2);
 682 +                                gen_helper_usat(tmp, cpu_env, tmp, tmp2);
 683                          } else {
 684                              /* Signed.  */
 685                              if ((op & 1) && shift == 0)
 686 -                                gen_helper_ssat16(tmp, tmp, tmp2);
 687 +                                gen_helper_ssat16(tmp, cpu_env, tmp, tmp2);
 688                              else
 689 -                                gen_helper_ssat(tmp, tmp, tmp2);
 690 +                                gen_helper_ssat(tmp, cpu_env, tmp, tmp2);
 691                          }
 692                          tcg_temp_free_i32(tmp2);
 693                          break;
 694 @@ -9017,12 +9017,12 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 695                  if (s->condexec_mask)
 696                      tcg_gen_sub_i32(tmp, tmp, tmp2);
 697                  else
 698 -                    gen_helper_sub_cc(tmp, tmp, tmp2);
 699 +                    gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 700              } else {
 701                  if (s->condexec_mask)
 702                      tcg_gen_add_i32(tmp, tmp, tmp2);
 703                  else
 704 -                    gen_helper_add_cc(tmp, tmp, tmp2);
 705 +                    gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
 706              }
 707              tcg_temp_free_i32(tmp2);
 708              store_reg(s, rd, tmp);
 709 @@ -9053,7 +9053,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 710              tcg_gen_movi_i32(tmp2, insn & 0xff);
 711              switch (op) {
 712              case 1: /* cmp */
 713 -                gen_helper_sub_cc(tmp, tmp, tmp2);
 714 +                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 715                  tcg_temp_free_i32(tmp);
 716                  tcg_temp_free_i32(tmp2);
 717                  break;
 718 @@ -9061,7 +9061,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 719                  if (s->condexec_mask)
 720                      tcg_gen_add_i32(tmp, tmp, tmp2);
 721                  else
 722 -                    gen_helper_add_cc(tmp, tmp, tmp2);
 723 +                    gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
 724                  tcg_temp_free_i32(tmp2);
 725                  store_reg(s, rd, tmp);
 726                  break;
 727 @@ -9069,7 +9069,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 728                  if (s->condexec_mask)
 729                      tcg_gen_sub_i32(tmp, tmp, tmp2);
 730                  else
 731 -                    gen_helper_sub_cc(tmp, tmp, tmp2);
 732 +                    gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 733                  tcg_temp_free_i32(tmp2);
 734                  store_reg(s, rd, tmp);
 735                  break;
 736 @@ -9105,7 +9105,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 737              case 1: /* cmp */
 738                  tmp = load_reg(s, rd);
 739                  tmp2 = load_reg(s, rm);
 740 -                gen_helper_sub_cc(tmp, tmp, tmp2);
 741 +                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 742                  tcg_temp_free_i32(tmp2);
 743                  tcg_temp_free_i32(tmp);
 744                  break;
 745 @@ -9166,25 +9166,25 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 746              break;
 747          case 0x2: /* lsl */
 748              if (s->condexec_mask) {
 749 -                gen_helper_shl(tmp2, tmp2, tmp);
 750 +                gen_helper_shl(tmp2, cpu_env, tmp2, tmp);
 751              } else {
 752 -                gen_helper_shl_cc(tmp2, tmp2, tmp);
 753 +                gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
 754                  gen_logic_CC(tmp2);
 755              }
 756              break;
 757          case 0x3: /* lsr */
 758              if (s->condexec_mask) {
 759 -                gen_helper_shr(tmp2, tmp2, tmp);
 760 +                gen_helper_shr(tmp2, cpu_env, tmp2, tmp);
 761              } else {
 762 -                gen_helper_shr_cc(tmp2, tmp2, tmp);
 763 +                gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
 764                  gen_logic_CC(tmp2);
 765              }
 766              break;
 767          case 0x4: /* asr */
 768              if (s->condexec_mask) {
 769 -                gen_helper_sar(tmp2, tmp2, tmp);
 770 +                gen_helper_sar(tmp2, cpu_env, tmp2, tmp);
 771              } else {
 772 -                gen_helper_sar_cc(tmp2, tmp2, tmp);
 773 +                gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
 774                  gen_logic_CC(tmp2);
 775              }
 776              break;
 777 @@ -9192,20 +9192,20 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 778              if (s->condexec_mask)
 779                  gen_adc(tmp, tmp2);
 780              else
 781 -                gen_helper_adc_cc(tmp, tmp, tmp2);
 782 +                gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2);
 783              break;
 784          case 0x6: /* sbc */
 785              if (s->condexec_mask)
 786                  gen_sub_carry(tmp, tmp, tmp2);
 787              else
 788 -                gen_helper_sbc_cc(tmp, tmp, tmp2);
 789 +                gen_helper_sbc_cc(tmp, cpu_env, tmp, tmp2);
 790              break;
 791          case 0x7: /* ror */
 792              if (s->condexec_mask) {
 793                  tcg_gen_andi_i32(tmp, tmp, 0x1f);
 794                  tcg_gen_rotr_i32(tmp2, tmp2, tmp);
 795              } else {
 796 -                gen_helper_ror_cc(tmp2, tmp2, tmp);
 797 +                gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
 798                  gen_logic_CC(tmp2);
 799              }
 800              break;
 801 @@ -9218,14 +9218,14 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
 802              if (s->condexec_mask)
 803                  tcg_gen_neg_i32(tmp, tmp2);
 804              else
 805 -                gen_helper_sub_cc(tmp, tmp, tmp2);
 806 +                gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 807              break;
 808          case 0xa: /* cmp */
 809 -            gen_helper_sub_cc(tmp, tmp, tmp2);
 810 +            gen_helper_sub_cc(tmp, cpu_env, tmp, tmp2);
 811              rd = 16;
 812              break;
 813          case 0xb: /* cmn */
 814 -            gen_helper_add_cc(tmp, tmp, tmp2);
 815 +            gen_helper_add_cc(tmp, cpu_env, tmp, tmp2);
 816              rd = 16;
 817              break;
 818          case 0xc: /* orr */
 819 --
 820 1.7.12.1
 821