1 From 140048c58e4ceb4f3bac87d7154d2731bb2bcd5d Mon Sep 17 00:00:00 2001
2 From: Blue Swirl <blauwirbel@gmail.com>
3 Date: Tue, 4 Sep 2012 20:08:34 +0000
4 Subject: [PATCH] target-arm: convert void helpers
6 Add an explicit CPUState parameter instead of relying on AREG0.
8 For easier review, convert only op helpers which don't return any value.
10 Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
11 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
14 target-arm/helper.h | 8 ++++----
15 target-arm/op_helper.c | 20 ++++++++++----------
16 target-arm/translate.c | 8 ++++----
17 3 files changed, 18 insertions(+), 18 deletions(-)
19 diff --git a/target-arm/helper.h b/target-arm/helper.h
20 index 21e9cfe..106aacd 100644
21 --- a/target-arm/helper.h
22 +++ b/target-arm/helper.h
23 @@ -50,10 +50,10 @@ DEF_HELPER_2(usad8, i32, i32, i32)
24 DEF_HELPER_1(logicq_cc, i32, i64)
26 DEF_HELPER_3(sel_flags, i32, i32, i32, i32)
27 -DEF_HELPER_1(exception, void, i32)
28 -DEF_HELPER_0(wfi, void)
29 +DEF_HELPER_2(exception, void, env, i32)
30 +DEF_HELPER_1(wfi, void, env)
32 -DEF_HELPER_2(cpsr_write, void, i32, i32)
33 +DEF_HELPER_3(cpsr_write, void, env, i32, i32)
34 DEF_HELPER_0(cpsr_read, i32)
36 DEF_HELPER_3(v7m_msr, void, env, i32, i32)
37 @@ -68,7 +68,7 @@ DEF_HELPER_2(get_r13_banked, i32, env, i32)
38 DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
40 DEF_HELPER_1(get_user_reg, i32, i32)
41 -DEF_HELPER_2(set_user_reg, void, i32, i32)
42 +DEF_HELPER_3(set_user_reg, void, env, i32, i32)
44 DEF_HELPER_1(vfp_get_fpscr, i32, env)
45 DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
46 diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
47 index d77bfab..b1adce3 100644
48 --- a/target-arm/op_helper.c
49 +++ b/target-arm/op_helper.c
51 #define SIGNBIT (uint32_t)0x80000000
52 #define SIGNBIT64 ((uint64_t)1 << 63)
54 -static void raise_exception(int tt)
55 +static void raise_exception(CPUARMState *env, int tt)
57 env->exception_index = tt;
59 @@ -93,7 +93,7 @@ void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
60 cpu_restore_state(tb, env, retaddr);
63 - raise_exception(env->exception_index);
64 + raise_exception(env, env->exception_index);
68 @@ -230,14 +230,14 @@ uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
72 -void HELPER(wfi)(void)
73 +void HELPER(wfi)(CPUARMState *env)
75 env->exception_index = EXCP_HLT;
80 -void HELPER(exception)(uint32_t excp)
81 +void HELPER(exception)(CPUARMState *env, uint32_t excp)
83 env->exception_index = excp;
85 @@ -248,7 +248,7 @@ uint32_t HELPER(cpsr_read)(void)
86 return cpsr_read(env) & ~CPSR_EXEC;
89 -void HELPER(cpsr_write)(uint32_t val, uint32_t mask)
90 +void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
92 cpsr_write(env, val, mask);
94 @@ -271,7 +271,7 @@ uint32_t HELPER(get_user_reg)(uint32_t regno)
98 -void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
99 +void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
102 env->banked_r13[0] = val;
103 @@ -290,7 +290,7 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
104 const ARMCPRegInfo *ri = rip;
105 int excp = ri->writefn(env, ri, value);
107 - raise_exception(excp);
108 + raise_exception(env, excp);
112 @@ -300,7 +300,7 @@ uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
114 int excp = ri->readfn(env, ri, &value);
116 - raise_exception(excp);
117 + raise_exception(env, excp);
121 @@ -310,7 +310,7 @@ void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
122 const ARMCPRegInfo *ri = rip;
123 int excp = ri->writefn(env, ri, value);
125 - raise_exception(excp);
126 + raise_exception(env, excp);
130 @@ -320,7 +320,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
132 int excp = ri->readfn(env, ri, &value);
134 - raise_exception(excp);
135 + raise_exception(env, excp);
139 diff --git a/target-arm/translate.c b/target-arm/translate.c
140 index edef79a..6f651d9 100644
141 --- a/target-arm/translate.c
142 +++ b/target-arm/translate.c
143 @@ -199,7 +199,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
144 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
146 TCGv tmp_mask = tcg_const_i32(mask);
147 - gen_helper_cpsr_write(var, tmp_mask);
148 + gen_helper_cpsr_write(cpu_env, var, tmp_mask);
149 tcg_temp_free_i32(tmp_mask);
151 /* Set NZCV flags from the high 4 bits of var. */
152 @@ -209,7 +209,7 @@ static void gen_exception(int excp)
154 TCGv tmp = tcg_temp_new_i32();
155 tcg_gen_movi_i32(tmp, excp);
156 - gen_helper_exception(tmp);
157 + gen_helper_exception(cpu_env, tmp);
158 tcg_temp_free_i32(tmp);
161 @@ -7719,7 +7719,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
162 tmp = gen_ld32(addr, IS_USER(s));
164 tmp2 = tcg_const_i32(i);
165 - gen_helper_set_user_reg(tmp2, tmp);
166 + gen_helper_set_user_reg(cpu_env, tmp2, tmp);
167 tcg_temp_free_i32(tmp2);
168 tcg_temp_free_i32(tmp);
169 } else if (i == rn) {
170 @@ -9913,7 +9913,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env,
171 /* nothing more to generate */
175 + gen_helper_wfi(cpu_env);
178 gen_exception(EXCP_SWI);