1 From 5560cd783146734a60c446f43227044cbb580edd Mon Sep 17 00:00:00 2001
2 From: Blue Swirl <blauwirbel@gmail.com>
3 Date: Sat, 8 Sep 2012 10:48:20 +0000
4 Subject: [PATCH] target-m68k: avoid using cpu_single_env
6 Pass around CPUState instead of using global cpu_single_env.
8 Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
9 Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
11 target-m68k/translate.c | 270 +++++++++++++++++++++++++-----------------------
12 1 file changed, 140 insertions(+), 130 deletions(-)
14 diff --git a/target-m68k/translate.c b/target-m68k/translate.c
15 index 10bb303..fb707f2 100644
16 --- a/target-m68k/translate.c
17 +++ b/target-m68k/translate.c
18 @@ -150,18 +150,24 @@ static void *gen_throws_exception;
22 -typedef void (*disas_proc)(DisasContext *, uint16_t);
23 +typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
26 -#define DISAS_INSN(name) \
27 - static void real_disas_##name (DisasContext *s, uint16_t insn); \
28 - static void disas_##name (DisasContext *s, uint16_t insn) { \
29 - qemu_log("Dispatch " #name "\n"); \
30 - real_disas_##name(s, insn); } \
31 - static void real_disas_##name (DisasContext *s, uint16_t insn)
32 +#define DISAS_INSN(name) \
33 + static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
35 + static void disas_##name(CPUM68KState *env, DisasContext *s, \
38 + qemu_log("Dispatch " #name "\n"); \
39 + real_disas_##name(s, env, insn); \
41 + static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
44 -#define DISAS_INSN(name) \
45 - static void disas_##name (DisasContext *s, uint16_t insn)
46 +#define DISAS_INSN(name) \
47 + static void disas_##name(CPUM68KState *env, DisasContext *s, \
51 /* Generate a load from the specified address. Narrow values are
52 @@ -257,12 +263,12 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
55 /* Read a 32-bit immediate constant. */
56 -static inline uint32_t read_im32(DisasContext *s)
57 +static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
60 - im = ((uint32_t)cpu_lduw_code(cpu_single_env, s->pc)) << 16;
61 + im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
63 - im |= cpu_lduw_code(cpu_single_env, s->pc);
64 + im |= cpu_lduw_code(env, s->pc);
68 @@ -288,7 +294,8 @@ static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
70 /* Handle a base + index + displacement effective addresss.
71 A NULL_QREG base means pc-relative. */
72 -static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
73 +static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize,
78 @@ -297,7 +304,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
82 - ext = cpu_lduw_code(cpu_single_env, s->pc);
83 + ext = cpu_lduw_code(env, s->pc);
86 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
87 @@ -311,10 +318,10 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
88 if ((ext & 0x30) > 0x10) {
89 /* base displacement */
90 if ((ext & 0x30) == 0x20) {
91 - bd = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
92 + bd = (int16_t)cpu_lduw_code(env, s->pc);
96 + bd = read_im32(env, s);
100 @@ -360,10 +367,10 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
102 /* outer displacement */
103 if ((ext & 3) == 2) {
104 - od = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
105 + od = (int16_t)cpu_lduw_code(env, s->pc);
109 + od = read_im32(env, s);
113 @@ -492,7 +499,8 @@ static inline TCGv gen_extend(TCGv val, int opsize, int sign)
115 /* Generate code for an "effective address". Does not adjust the base
116 register for autoincrement addressing modes. */
117 -static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
118 +static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
123 @@ -514,29 +522,29 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
124 case 5: /* Indirect displacement. */
126 tmp = tcg_temp_new();
127 - ext = cpu_lduw_code(cpu_single_env, s->pc);
128 + ext = cpu_lduw_code(env, s->pc);
130 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
132 case 6: /* Indirect index + displacement. */
134 - return gen_lea_indexed(s, opsize, reg);
135 + return gen_lea_indexed(env, s, opsize, reg);
138 case 0: /* Absolute short. */
139 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
140 + offset = cpu_ldsw_code(env, s->pc);
142 return tcg_const_i32(offset);
143 case 1: /* Absolute long. */
144 - offset = read_im32(s);
145 + offset = read_im32(env, s);
146 return tcg_const_i32(offset);
147 case 2: /* pc displacement */
149 - offset += cpu_ldsw_code(cpu_single_env, s->pc);
150 + offset += cpu_ldsw_code(env, s->pc);
152 return tcg_const_i32(offset);
153 case 3: /* pc index+displacement. */
154 - return gen_lea_indexed(s, opsize, NULL_QREG);
155 + return gen_lea_indexed(env, s, opsize, NULL_QREG);
156 case 4: /* Immediate. */
159 @@ -548,15 +556,16 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
161 /* Helper function for gen_ea. Reuse the computed address between the
162 for read/write operands. */
163 -static inline TCGv gen_ea_once(DisasContext *s, uint16_t insn, int opsize,
164 - TCGv val, TCGv *addrp, ea_what what)
165 +static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
166 + uint16_t insn, int opsize, TCGv val,
167 + TCGv *addrp, ea_what what)
171 if (addrp && what == EA_STORE) {
174 - tmp = gen_lea(s, insn, opsize);
175 + tmp = gen_lea(env, s, insn, opsize);
176 if (IS_NULL_QREG(tmp))
179 @@ -568,8 +577,8 @@ static inline TCGv gen_ea_once(DisasContext *s, uint16_t insn, int opsize,
180 /* Generate code to load/store a value ito/from an EA. If VAL > 0 this is
181 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
182 ADDRP is non-null for readwrite operands. */
183 -static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
184 - TCGv *addrp, ea_what what)
185 +static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
186 + int opsize, TCGv val, TCGv *addrp, ea_what what)
190 @@ -609,7 +618,7 @@ static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
191 if (addrp && what == EA_STORE) {
194 - tmp = gen_lea(s, insn, opsize);
195 + tmp = gen_lea(env, s, insn, opsize);
196 if (IS_NULL_QREG(tmp))
199 @@ -626,35 +635,35 @@ static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
201 case 5: /* Indirect displacement. */
202 case 6: /* Indirect index + displacement. */
203 - return gen_ea_once(s, insn, opsize, val, addrp, what);
204 + return gen_ea_once(env, s, insn, opsize, val, addrp, what);
207 case 0: /* Absolute short. */
208 case 1: /* Absolute long. */
209 case 2: /* pc displacement */
210 case 3: /* pc index+displacement. */
211 - return gen_ea_once(s, insn, opsize, val, addrp, what);
212 + return gen_ea_once(env, s, insn, opsize, val, addrp, what);
213 case 4: /* Immediate. */
214 /* Sign extend values for consistency. */
217 if (what == EA_LOADS) {
218 - offset = cpu_ldsb_code(cpu_single_env, s->pc + 1);
219 + offset = cpu_ldsb_code(env, s->pc + 1);
221 - offset = cpu_ldub_code(cpu_single_env, s->pc + 1);
222 + offset = cpu_ldub_code(env, s->pc + 1);
227 if (what == EA_LOADS) {
228 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
229 + offset = cpu_ldsw_code(env, s->pc);
231 - offset = cpu_lduw_code(cpu_single_env, s->pc);
232 + offset = cpu_lduw_code(env, s->pc);
237 - offset = read_im32(s);
238 + offset = read_im32(env, s);
241 qemu_assert(0, "Bad immediate operand");
242 @@ -825,20 +834,21 @@ static inline void gen_addr_fault(DisasContext *s)
243 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
246 -#define SRC_EA(result, opsize, op_sign, addrp) do { \
247 - result = gen_ea(s, insn, opsize, NULL_QREG, addrp, op_sign ? EA_LOADS : EA_LOADU); \
248 - if (IS_NULL_QREG(result)) { \
249 - gen_addr_fault(s); \
252 +#define SRC_EA(env, result, opsize, op_sign, addrp) do { \
253 + result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
254 + op_sign ? EA_LOADS : EA_LOADU); \
255 + if (IS_NULL_QREG(result)) { \
256 + gen_addr_fault(s); \
261 -#define DEST_EA(insn, opsize, val, addrp) do { \
262 - TCGv ea_result = gen_ea(s, insn, opsize, val, addrp, EA_STORE); \
263 - if (IS_NULL_QREG(ea_result)) { \
264 - gen_addr_fault(s); \
267 +#define DEST_EA(env, insn, opsize, val, addrp) do { \
268 + TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
269 + if (IS_NULL_QREG(ea_result)) { \
270 + gen_addr_fault(s); \
275 /* Generate a jump to an immediate address. */
276 @@ -874,8 +884,7 @@ DISAS_INSN(undef_fpu)
279 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
280 - cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",
282 + cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
286 @@ -892,7 +901,7 @@ DISAS_INSN(mulw)
287 tcg_gen_ext16s_i32(tmp, reg);
289 tcg_gen_ext16u_i32(tmp, reg);
290 - SRC_EA(src, OS_WORD, sign, NULL);
291 + SRC_EA(env, src, OS_WORD, sign, NULL);
292 tcg_gen_mul_i32(tmp, tmp, src);
293 tcg_gen_mov_i32(reg, tmp);
294 /* Unlike m68k, coldfire always clears the overflow bit. */
295 @@ -913,7 +922,7 @@ DISAS_INSN(divw)
297 tcg_gen_ext16u_i32(QREG_DIV1, reg);
299 - SRC_EA(src, OS_WORD, sign, NULL);
300 + SRC_EA(env, src, OS_WORD, sign, NULL);
301 tcg_gen_mov_i32(QREG_DIV2, src);
303 gen_helper_divs(cpu_env, tcg_const_i32(1));
304 @@ -936,7 +945,7 @@ DISAS_INSN(divl)
308 - ext = cpu_lduw_code(cpu_single_env, s->pc);
309 + ext = cpu_lduw_code(env, s->pc);
312 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
313 @@ -945,7 +954,7 @@ DISAS_INSN(divl)
316 tcg_gen_mov_i32(QREG_DIV1, num);
317 - SRC_EA(den, OS_LONG, 0, NULL);
318 + SRC_EA(env, den, OS_LONG, 0, NULL);
319 tcg_gen_mov_i32(QREG_DIV2, den);
321 gen_helper_divs(cpu_env, tcg_const_i32(0));
322 @@ -975,11 +984,11 @@ DISAS_INSN(addsub)
324 dest = tcg_temp_new();
326 - SRC_EA(tmp, OS_LONG, 0, &addr);
327 + SRC_EA(env, tmp, OS_LONG, 0, &addr);
331 - SRC_EA(src, OS_LONG, 0, NULL);
332 + SRC_EA(env, src, OS_LONG, 0, NULL);
335 tcg_gen_add_i32(dest, tmp, src);
336 @@ -992,7 +1001,7 @@ DISAS_INSN(addsub)
338 gen_update_cc_add(dest, src);
340 - DEST_EA(insn, OS_LONG, dest, &addr);
341 + DEST_EA(env, insn, OS_LONG, dest, &addr);
343 tcg_gen_mov_i32(reg, dest);
345 @@ -1022,7 +1031,7 @@ DISAS_INSN(bitop_reg)
348 op = (insn >> 6) & 3;
349 - SRC_EA(src1, opsize, 0, op ? &addr: NULL);
350 + SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
351 src2 = DREG(insn, 9);
352 dest = tcg_temp_new();
354 @@ -1057,7 +1066,7 @@ DISAS_INSN(bitop_reg)
358 - DEST_EA(insn, opsize, dest, &addr);
359 + DEST_EA(env, insn, opsize, dest, &addr);
363 @@ -1088,9 +1097,9 @@ DISAS_INSN(movem)
367 - mask = cpu_lduw_code(cpu_single_env, s->pc);
368 + mask = cpu_lduw_code(env, s->pc);
370 - tmp = gen_lea(s, insn, OS_LONG);
371 + tmp = gen_lea(env, s, insn, OS_LONG);
372 if (IS_NULL_QREG(tmp)) {
375 @@ -1132,14 +1141,14 @@ DISAS_INSN(bitop_im)
377 op = (insn >> 6) & 3;
379 - bitnum = cpu_lduw_code(cpu_single_env, s->pc);
380 + bitnum = cpu_lduw_code(env, s->pc);
382 if (bitnum & 0xff00) {
383 - disas_undef(s, insn);
384 + disas_undef(env, s, insn);
388 - SRC_EA(src1, opsize, 0, op ? &addr: NULL);
389 + SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
392 if (opsize == OS_BYTE)
393 @@ -1174,7 +1183,7 @@ DISAS_INSN(bitop_im)
397 - DEST_EA(insn, opsize, tmp, &addr);
398 + DEST_EA(env, insn, opsize, tmp, &addr);
402 @@ -1187,8 +1196,8 @@ DISAS_INSN(arith_im)
405 op = (insn >> 9) & 7;
406 - SRC_EA(src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
408 + SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
409 + im = read_im32(env, s);
410 dest = tcg_temp_new();
413 @@ -1227,7 +1236,7 @@ DISAS_INSN(arith_im)
417 - DEST_EA(insn, OS_LONG, dest, &addr);
418 + DEST_EA(env, insn, OS_LONG, dest, &addr);
422 @@ -1259,7 +1268,7 @@ DISAS_INSN(move)
426 - SRC_EA(src, opsize, 1, NULL);
427 + SRC_EA(env, src, opsize, 1, NULL);
428 op = (insn >> 6) & 7;
431 @@ -1270,7 +1279,7 @@ DISAS_INSN(move)
434 dest_ea = ((insn >> 9) & 7) | (op << 3);
435 - DEST_EA(dest_ea, opsize, src, NULL);
436 + DEST_EA(env, dest_ea, opsize, src, NULL);
437 /* This will be correct because loads sign extend. */
438 gen_logic_cc(s, src);
440 @@ -1291,7 +1300,7 @@ DISAS_INSN(lea)
444 - tmp = gen_lea(s, insn, OS_LONG);
445 + tmp = gen_lea(env, s, insn, OS_LONG);
446 if (IS_NULL_QREG(tmp)) {
449 @@ -1316,7 +1325,7 @@ DISAS_INSN(clr)
453 - DEST_EA(insn, opsize, tcg_const_i32(0), NULL);
454 + DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
455 gen_logic_cc(s, tcg_const_i32(0));
458 @@ -1365,7 +1374,8 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
462 -static void gen_set_sr(DisasContext *s, uint16_t insn, int ccr_only)
463 +static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
468 @@ -1385,17 +1395,17 @@ static void gen_set_sr(DisasContext *s, uint16_t insn, int ccr_only)
469 else if ((insn & 0x3f) == 0x3c)
472 - val = cpu_lduw_code(cpu_single_env, s->pc);
473 + val = cpu_lduw_code(env, s->pc);
475 gen_set_sr_im(s, val, ccr_only);
478 - disas_undef(s, insn);
479 + disas_undef(env, s, insn);
482 DISAS_INSN(move_to_ccr)
484 - gen_set_sr(s, insn, 1);
485 + gen_set_sr(env, s, insn, 1);
489 @@ -1426,7 +1436,7 @@ DISAS_INSN(pea)
493 - tmp = gen_lea(s, insn, OS_LONG);
494 + tmp = gen_lea(env, s, insn, OS_LONG);
495 if (IS_NULL_QREG(tmp)) {
498 @@ -1472,7 +1482,7 @@ DISAS_INSN(tst)
502 - SRC_EA(tmp, opsize, 1, NULL);
503 + SRC_EA(env, tmp, opsize, 1, NULL);
504 gen_logic_cc(s, tmp);
507 @@ -1494,10 +1504,10 @@ DISAS_INSN(tas)
510 dest = tcg_temp_new();
511 - SRC_EA(src1, OS_BYTE, 1, &addr);
512 + SRC_EA(env, src1, OS_BYTE, 1, &addr);
513 gen_logic_cc(s, src1);
514 tcg_gen_ori_i32(dest, src1, 0x80);
515 - DEST_EA(insn, OS_BYTE, dest, &addr);
516 + DEST_EA(env, insn, OS_BYTE, dest, &addr);
520 @@ -1509,14 +1519,14 @@ DISAS_INSN(mull)
522 /* The upper 32 bits of the product are discarded, so
523 muls.l and mulu.l are functionally equivalent. */
524 - ext = cpu_lduw_code(cpu_single_env, s->pc);
525 + ext = cpu_lduw_code(env, s->pc);
528 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
532 - SRC_EA(src1, OS_LONG, 0, NULL);
533 + SRC_EA(env, src1, OS_LONG, 0, NULL);
534 dest = tcg_temp_new();
535 tcg_gen_mul_i32(dest, src1, reg);
536 tcg_gen_mov_i32(reg, dest);
537 @@ -1530,7 +1540,7 @@ DISAS_INSN(link)
541 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
542 + offset = cpu_ldsw_code(env, s->pc);
545 tmp = tcg_temp_new();
546 @@ -1574,7 +1584,7 @@ DISAS_INSN(jump)
548 /* Load the target address first to ensure correct exception
550 - tmp = gen_lea(s, insn, OS_LONG);
551 + tmp = gen_lea(env, s, insn, OS_LONG);
552 if (IS_NULL_QREG(tmp)) {
555 @@ -1594,7 +1604,7 @@ DISAS_INSN(addsubq)
559 - SRC_EA(src1, OS_LONG, 0, &addr);
560 + SRC_EA(env, src1, OS_LONG, 0, &addr);
561 val = (insn >> 9) & 7;
564 @@ -1621,7 +1631,7 @@ DISAS_INSN(addsubq)
566 gen_update_cc_add(dest, src2);
568 - DEST_EA(insn, OS_LONG, dest, &addr);
569 + DEST_EA(env, insn, OS_LONG, dest, &addr);
573 @@ -1636,7 +1646,7 @@ DISAS_INSN(tpf)
574 case 4: /* No extension words. */
577 - disas_undef(s, insn);
578 + disas_undef(env, s, insn);
582 @@ -1651,10 +1661,10 @@ DISAS_INSN(branch)
583 op = (insn >> 8) & 0xf;
584 offset = (int8_t)insn;
586 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
587 + offset = cpu_ldsw_code(env, s->pc);
589 } else if (offset == -1) {
590 - offset = read_im32(s);
591 + offset = read_im32(env, s);
595 @@ -1693,7 +1703,7 @@ DISAS_INSN(mvzs)
599 - SRC_EA(src, opsize, (insn & 0x80) == 0, NULL);
600 + SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
602 tcg_gen_mov_i32(reg, src);
603 gen_logic_cc(s, src);
604 @@ -1709,11 +1719,11 @@ DISAS_INSN(or)
606 dest = tcg_temp_new();
608 - SRC_EA(src, OS_LONG, 0, &addr);
609 + SRC_EA(env, src, OS_LONG, 0, &addr);
610 tcg_gen_or_i32(dest, src, reg);
611 - DEST_EA(insn, OS_LONG, dest, &addr);
612 + DEST_EA(env, insn, OS_LONG, dest, &addr);
614 - SRC_EA(src, OS_LONG, 0, NULL);
615 + SRC_EA(env, src, OS_LONG, 0, NULL);
616 tcg_gen_or_i32(dest, src, reg);
617 tcg_gen_mov_i32(reg, dest);
619 @@ -1725,7 +1735,7 @@ DISAS_INSN(suba)
623 - SRC_EA(src, OS_LONG, 0, NULL);
624 + SRC_EA(env, src, OS_LONG, 0, NULL);
626 tcg_gen_sub_i32(reg, reg, src);
628 @@ -1751,7 +1761,7 @@ DISAS_INSN(mov3q)
630 src = tcg_const_i32(val);
631 gen_logic_cc(s, src);
632 - DEST_EA(insn, OS_LONG, src, NULL);
633 + DEST_EA(env, insn, OS_LONG, src, NULL);
637 @@ -1779,7 +1789,7 @@ DISAS_INSN(cmp)
641 - SRC_EA(src, opsize, 1, NULL);
642 + SRC_EA(env, src, opsize, 1, NULL);
644 dest = tcg_temp_new();
645 tcg_gen_sub_i32(dest, reg, src);
646 @@ -1798,7 +1808,7 @@ DISAS_INSN(cmpa)
650 - SRC_EA(src, opsize, 1, NULL);
651 + SRC_EA(env, src, opsize, 1, NULL);
653 dest = tcg_temp_new();
654 tcg_gen_sub_i32(dest, reg, src);
655 @@ -1813,12 +1823,12 @@ DISAS_INSN(eor)
659 - SRC_EA(src, OS_LONG, 0, &addr);
660 + SRC_EA(env, src, OS_LONG, 0, &addr);
662 dest = tcg_temp_new();
663 tcg_gen_xor_i32(dest, src, reg);
664 gen_logic_cc(s, dest);
665 - DEST_EA(insn, OS_LONG, dest, &addr);
666 + DEST_EA(env, insn, OS_LONG, dest, &addr);
670 @@ -1831,11 +1841,11 @@ DISAS_INSN(and)
672 dest = tcg_temp_new();
674 - SRC_EA(src, OS_LONG, 0, &addr);
675 + SRC_EA(env, src, OS_LONG, 0, &addr);
676 tcg_gen_and_i32(dest, src, reg);
677 - DEST_EA(insn, OS_LONG, dest, &addr);
678 + DEST_EA(env, insn, OS_LONG, dest, &addr);
680 - SRC_EA(src, OS_LONG, 0, NULL);
681 + SRC_EA(env, src, OS_LONG, 0, NULL);
682 tcg_gen_and_i32(dest, src, reg);
683 tcg_gen_mov_i32(reg, dest);
685 @@ -1847,7 +1857,7 @@ DISAS_INSN(adda)
689 - SRC_EA(src, OS_LONG, 0, NULL);
690 + SRC_EA(env, src, OS_LONG, 0, NULL);
692 tcg_gen_add_i32(reg, reg, src);
694 @@ -1936,13 +1946,13 @@ DISAS_INSN(strldsr)
698 - ext = cpu_lduw_code(cpu_single_env, s->pc);
699 + ext = cpu_lduw_code(env, s->pc);
702 gen_exception(s, addr, EXCP_UNSUPPORTED);
705 - ext = cpu_lduw_code(cpu_single_env, s->pc);
706 + ext = cpu_lduw_code(env, s->pc);
708 if (IS_USER(s) || (ext & SR_S) == 0) {
709 gen_exception(s, addr, EXCP_PRIVILEGE);
710 @@ -1972,7 +1982,7 @@ DISAS_INSN(move_to_sr)
711 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
714 - gen_set_sr(s, insn, 0);
715 + gen_set_sr(env, s, insn, 0);
719 @@ -2010,7 +2020,7 @@ DISAS_INSN(stop)
723 - ext = cpu_lduw_code(cpu_single_env, s->pc);
724 + ext = cpu_lduw_code(env, s->pc);
727 gen_set_sr_im(s, ext, 0);
728 @@ -2037,7 +2047,7 @@ DISAS_INSN(movec)
732 - ext = cpu_lduw_code(cpu_single_env, s->pc);
733 + ext = cpu_lduw_code(env, s->pc);
737 @@ -2102,7 +2112,7 @@ DISAS_INSN(fpu)
741 - ext = cpu_lduw_code(cpu_single_env, s->pc);
742 + ext = cpu_lduw_code(env, s->pc);
745 switch ((ext >> 13) & 7) {
746 @@ -2138,7 +2148,7 @@ DISAS_INSN(fpu)
747 tcg_gen_addi_i32(tmp32, tmp32, -8);
750 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
751 + offset = cpu_ldsw_code(env, s->pc);
753 tcg_gen_addi_i32(tmp32, tmp32, offset);
755 @@ -2164,7 +2174,7 @@ DISAS_INSN(fpu)
759 - DEST_EA(insn, opsize, tmp32, NULL);
760 + DEST_EA(env, insn, opsize, tmp32, NULL);
761 tcg_temp_free_i32(tmp32);
763 case 4: /* fmove to control register. */
764 @@ -2192,7 +2202,7 @@ DISAS_INSN(fpu)
768 - DEST_EA(insn, OS_LONG, tmp32, NULL);
769 + DEST_EA(env, insn, OS_LONG, tmp32, NULL);
773 @@ -2202,7 +2212,7 @@ DISAS_INSN(fpu)
775 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
777 - tmp32 = gen_lea(s, insn, OS_LONG);
778 + tmp32 = gen_lea(env, s, insn, OS_LONG);
779 if (IS_NULL_QREG(tmp32)) {
782 @@ -2252,12 +2262,12 @@ DISAS_INSN(fpu)
783 tcg_gen_addi_i32(tmp32, tmp32, -8);
786 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
787 + offset = cpu_ldsw_code(env, s->pc);
789 tcg_gen_addi_i32(tmp32, tmp32, offset);
792 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
793 + offset = cpu_ldsw_code(env, s->pc);
796 tcg_gen_addi_i32(tmp32, tmp32, offset);
797 @@ -2277,7 +2287,7 @@ DISAS_INSN(fpu)
799 tcg_temp_free_i32(tmp32);
801 - SRC_EA(tmp32, opsize, 1, NULL);
802 + SRC_EA(env, tmp32, opsize, 1, NULL);
803 src = tcg_temp_new_i64();
806 @@ -2372,7 +2382,7 @@ DISAS_INSN(fpu)
808 /* FIXME: Is this right for offset addressing modes? */
810 - disas_undef_fpu(s, insn);
811 + disas_undef_fpu(env, s, insn);
815 @@ -2383,10 +2393,10 @@ DISAS_INSN(fbcc)
819 - offset = cpu_ldsw_code(cpu_single_env, s->pc);
820 + offset = cpu_ldsw_code(env, s->pc);
822 if (insn & (1 << 6)) {
823 - offset = (offset << 16) | cpu_lduw_code(cpu_single_env, s->pc);
824 + offset = (offset << 16) | cpu_lduw_code(env, s->pc);
828 @@ -2508,18 +2518,18 @@ DISAS_INSN(mac)
832 - ext = cpu_lduw_code(cpu_single_env, s->pc);
833 + ext = cpu_lduw_code(env, s->pc);
836 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
837 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
838 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
839 - disas_undef(s, insn);
840 + disas_undef(env, s, insn);
845 - tmp = gen_lea(s, insn, OS_LONG);
846 + tmp = gen_lea(env, s, insn, OS_LONG);
847 addr = tcg_temp_new();
848 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
849 /* Load the value now to ensure correct exception behavior.
850 @@ -2733,7 +2743,7 @@ DISAS_INSN(to_mac)
852 accnum = (insn >> 9) & 3;
853 acc = MACREG(accnum);
854 - SRC_EA(val, OS_LONG, 0, NULL);
855 + SRC_EA(env, val, OS_LONG, 0, NULL);
856 if (s->env->macsr & MACSR_FI) {
857 tcg_gen_ext_i32_i64(acc, val);
858 tcg_gen_shli_i64(acc, acc, 8);
859 @@ -2750,7 +2760,7 @@ DISAS_INSN(to_mac)
863 - SRC_EA(val, OS_LONG, 0, NULL);
864 + SRC_EA(env, val, OS_LONG, 0, NULL);
865 gen_helper_set_macsr(cpu_env, val);
868 @@ -2758,7 +2768,7 @@ DISAS_INSN(to_macsr)
872 - SRC_EA(val, OS_LONG, 0, NULL);
873 + SRC_EA(env, val, OS_LONG, 0, NULL);
874 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
877 @@ -2766,7 +2776,7 @@ DISAS_INSN(to_mext)
881 - SRC_EA(val, OS_LONG, 0, NULL);
882 + SRC_EA(env, val, OS_LONG, 0, NULL);
883 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
884 if (s->env->macsr & MACSR_FI)
885 gen_helper_set_mac_extf(cpu_env, val, acc);
886 @@ -2943,10 +2953,10 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
890 - insn = cpu_lduw_code(cpu_single_env, s->pc);
891 + insn = cpu_lduw_code(env, s->pc);
894 - opcode_table[insn](s, insn);
895 + opcode_table[insn](env, s, insn);
898 /* generate intermediate code for basic block 'tb'. */